Intel BFCBASE Data Sheet - Page 49
FSB Source Synchronous 2X Address Timing Waveform
UPC - 735858197373
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Electrical Specifications Figure 2-17. FSB Source Synchronous 2X (Address) Timing Waveform T0 BCLK1 BCLK0 ADSTB# (@ driver) Tp/4 Tp/2 3Tp/4 T1 TR A# (@ driver) TH TJ valid TH TJ valid TS ADSTB# (@ receiver) T2 TK A# (@ receiver) valid valid TM TN TP = T1: BCLK[1:0] Period TH = T23: Source Sync. Address Output Valid Before Address Strobe TJ = T24: Source Sync. Address Output Valid After Address Strobe TK = T27: Source Sync. Address Strobe Setup Time to BCLK TM = T25: Source Sync. Input Setup Time TN = T26: Source Sync. Input Hold Time TS = T20: Source Sync. Output Valid Delay TR = T31: Address Strobe Output Valid Delay Document Number: 318080-002 49
Document Number: 318080-002
49
Electrical Specifications
Figure 2-17. FSB Source Synchronous 2X (Address) Timing Waveform
T
p
/4
T
p
/2
3T
p
/4
BCLK0
BCLK1
ADSTB# (@ driver)
A# (@ driver)
A# (@
receiver)
ADSTB# (@ receiver)
valid
valid
valid
valid
T
M
T
N
T
K
T
S
T
H
T
J
T
H
T
J
T
H
= T23: Source Sync. Address Output Valid Before Address Strobe
T
J
= T24: Source Sync. Address Output Valid After Address Strobe
T
K
= T27: Source Sync. Address Strobe Setup Time to BCLK
T
M
= T25: Source Sync. Input Setup Time
T
N
= T26: Source Sync. Input Hold Time
T
S
= T20: Source Sync. Output Valid Delay
T
P
= T1: BCLK[1:0] Period
T
R
T
R
= T31: Address Strobe Output Valid Delay
T0
T1
T2