Intel BFCBASE Data Sheet - Page 39

Table 2-17., AGTL+ Bus Voltage Definitions, FSB Differential BCLK Specifications, Symbol, Parameter

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Electrical Specifications Table 2-17. AGTL+ Bus Voltage Definitions Symbol GTLREF_DATA_MID GTLREF_DATA_END GTLREF_ADD_MID GTLREF_ADD_END RTT COMP Parameter Data Bus Reference Voltage Address Bus Reference Voltage Termination Resistance (pull up) COMP Resistance Min 0.98 * 0.67 * VTT 0.98 * 0.67 * VTT 45 49.4 Typ 0.67 * VTT 0.67 * VTT 50 49.9 Max 1.02 * 0.67 * VTT 1.02 * 0.67 * VTT 55 50.4 Units V Notes1 2, 3 V 2, 3 Ω 4 Ω 5 Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. The tolerances for this specification have been stated generically to enable system designer to calculate the minimum values across the range of VTT. 3. GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END is generated from VTT on the baseboard by a voltage divider of 1% resistors. The minimum and maximum specifications account for this resistor tolerance. Refer to the appropriate platform design guidelines for implementation details. The VTT referred to in these specifications is the instantaneous VTT. 4. RTT is the on-die termination resistance measured at VOL of the AGTL+ output driver. Measured at 0.31*VTT. RTT is connected to VTT on die. Refer to processor I/O Buffer Models for I/V characteristics. 5. COMP resistance must be provided on the system board with +/- 1% resistors. See the applicable platform design guide for implementation details. Table 2-18. FSB Differential BCLK Specifications Symbol VIL VIH VCROSS(abs) VCROSS(rel) Δ VCROSS Parameter Single-ended Input Low Voltage Single-ended Input High Voltage Absolute Crossing Point Relative Crossing Point Vcross variation Min -0.150 Typ 0.0 Max 0.15 Unit V 0.660 0.710 0.850 V 0.250 0.350 0.550 V 0.250 + N/A 0.550 + V 0.5 * (VHavg - 0.700) 0.5 * (VHavg - 0.700) N/A N/A 0.140 V VMAX (Absolute Overshoot) VMIN (Absolute Undershoot) VRBM VTR ILI Single-ended maximum voltage Single-ended minimum voltage Single-ended Ringback Margin Single-ended Threshold Region Input Leakage Current N/A -0.300 0.200 VCROSS - 0.100 N/A N/A 1.15 V N/A N/A V N/A N/A V N/A VCROSS + 0.100 V N/A +/- 100 μA Figure 2-13 Notes1,2 2-13 2-13, 2-14 2-13, 2-14 2-13, 2-14 2-13 2,8 3,8,9, 11 4 2-13 5 2-13 6 2-13 7 10 Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Crossing Voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 is equal to the falling edge of BCLK1. 3. VHavg is the statistical average of the VH measured by the oscilloscope. 4. Overshoot is defined as the absolute value of the maximum voltage. 5. Undershoot is defined as the absolute value of the minimum voltage. 6. Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback and the maximum Falling Edge Ringback. 7. Threshold Region is defined as a region entered around the crossing point voltage in which the differential receiver switches. It includes input threshold hysteresis. 8. The crossing point must meet the absolute and relative crossing point specifications simultaneously. 9. VHavg can be measured directly using "Vtop" on Agilent and "High" on Tektronix oscilloscopes. 10. For VIN between 0 V and VHΔVCROSS is defined as the total variation of all crossing voltages as defined in note 2. Document Number: 318080-002 39

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Document Number: 318080-002
39
Electrical Specifications
Notes:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
The tolerances for this specification have been stated generically to enable system designer to calculate the minimum values
across the range of V
TT
.
3.
GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END is generated from V
TT
on the
baseboard by a voltage divider of 1% resistors. The minimum and maximum specifications account for this resistor tolerance.
Refer to the appropriate platform design guidelines for implementation details. The V
TT
referred to in these specifications is
the instantaneous V
TT
.
4.
R
TT
is the on-die termination resistance measured at V
OL
of the AGTL+ output driver. Measured at 0.31*V
TT
. R
TT
is connected
to V
TT
on die. Refer to processor I/O Buffer Models for I/V characteristics.
5.
COMP resistance must be provided on the system board with +/- 1% resistors. See the applicable platform design guide for
implementation details.
Notes:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
Crossing Voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 is equal to the falling edge of
BCLK1.
3.
V
Havg
is the statistical average of the V
H
measured by the oscilloscope.
4.
Overshoot is defined as the absolute value of the maximum voltage.
5.
Undershoot is defined as the absolute value of the minimum voltage.
6.
Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback and the maximum
Falling Edge Ringback.
7.
Threshold Region is defined as a region entered around the crossing point voltage in which the differential receiver switches.
It includes input threshold hysteresis.
8.
The crossing point must meet the absolute and relative crossing point specifications simultaneously.
9.
V
Havg
can be measured directly using “Vtop” on Agilent and “High” on Tektronix oscilloscopes.
10.
For V
IN
between 0 V and V
H
Δ
V
CROSS
is defined as the total variation of all crossing voltages as defined in note 2.
Table 2-17.
AGTL+ Bus Voltage Definitions
Symbol
Parameter
Min
Typ
Max
Units
Notes
1
GTLREF_DATA_MID
GTLREF_DATA_END
Data Bus Reference
Voltage
0.98 * 0.67 * V
TT
0.67 * V
TT
1.02 * 0.67 * V
TT
V
2, 3
GTLREF_ADD_MID
GTLREF_ADD_END
Address Bus
Reference Voltage
0.98 * 0.67 * V
TT
0.67 * V
TT
1.02 * 0.67 * V
TT
V
2, 3
R
TT
Termination
Resistance (pull up)
45
50
55
Ω
4
COMP
COMP Resistance
49.4
49.9
50.4
Ω
5
Table 2-18.
FSB Differential BCLK Specifications
Symbol
Parameter
Min
Typ
Max
Unit
Figure
Notes
1,2
V
IL
Single-ended Input
Low Voltage
-0.150
0.0
0.15
V
2-13
V
IH
Single-ended Input
High Voltage
0.660
0.710
0.850
V
2-13
V
CROSS(abs)
Absolute Crossing
Point
0.250
0.350
0.550
V
2-13,
2-14
2,8
V
CROSS(rel)
Relative Crossing
Point
0.250 +
0.5 * (V
Havg
- 0.700)
N/A
0.550 +
0.5 * (V
Havg
- 0.700)
V
2-13,
2-14
3,8,9, 11
Δ
V
CROSS
Vcross variation
N/A
N/A
0.140
V
2-13,
2-14
V
MAX (Absolute
Overshoot)
Single-ended
maximum voltage
N/A
N/A
1.15
V
2-13
4
V
MIN (Absolute
Undershoot)
Single-ended
minimum voltage
-0.300
N/A
N/A
V
2-13
5
V
RBM
Single-ended
Ringback Margin
0.200
N/A
N/A
V
2-13
6
V
TR
Single-ended
Threshold Region
V
CROSS
- 0.100
N/A
V
CROSS
+ 0.100
V
2-13
7
I
LI
Input Leakage
Current
N/A
N/A
+/- 100
μ
A
10