Intel BFCBASE Data Sheet - Page 32

Quad-Core Intel® Xeon® X7350 Processor VCC Static and Transient Tolerance, Load Lines

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Electrical Specifications Figure 2-6. Quad-Core Intel® Xeon® X7350 Processor VCC Static and Transient Tolerance Load Lines 0 V ID - 0.000 Icc [A] 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130 V ID - 0.050 VCC M axim um V ID - 0.100 Vcc [V] V ID - 0.150 V ID - 0.200 VCC Ty pic al VCC M inim um V ID - 0.250 Notes: 1. The VCC_MIN and VCC_MAX loadlines represent static and transient limits. Please see Section 2.11.3 for VCC overshoot specifications. 2. Refer to Table 2-9 for processor VID information. 3. Refer to Table 2-10 for VCCStatic and Transient Tolerance 4. The load lines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE pins and the VCC_SENSE2 and VSS_SENSE2 pins. Voltage regulation feedback for voltage regulator circuits must also be taken from processor VCC_SENSE2 and VSS_SENSE2 pins. Refer to the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator Down (EVRD) 11.0 Design Guidelines for socket load line guidelines and VR implementation. Please refer to the appropriate platform design guide for details on VR implementation. 32 Document Number: 318080-002

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Electrical Specifications
32
Document Number: 318080-002
Notes:
1.
The V
CC_MIN
and V
CC_MAX
loadlines represent static and transient limits. Please see
Section 2.11.3
for VCC
overshoot specifications.
2.
Refer to
Table 2-9
for processor VID information.
3.
Refer to
Table 2-10
for V
CC
Static and Transient Tolerance
4.
The load lines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE pins and the
VCC_SENSE2 and VSS_SENSE2 pins. Voltage regulation feedback for voltage regulator circuits must also
be taken from processor VCC_SENSE2 and VSS_SENSE2 pins. Refer to the
Voltage Regulator Module
(VRM) and Enterprise Voltage Regulator Down (EVRD) 11.0 Design Guidelines
for socket load line
guidelines and VR implementation. Please refer to the appropriate platform design guide for details on VR
implementation.
Figure 2-6.
Quad-Core Intel® Xeon® X7350 Processor VCC Static and Transient Tolerance
Load Lines
VID - 0.000
VID - 0.050
VID - 0.100
VID - 0.150
VID - 0.200
VID - 0.250
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
105
110
115
120
125
130
Icc [A]
Vcc [V]
V
CC
Maximum
V
CC
Typical
V
CC
Minimum