Intel BFCBASE Data Sheet - Page 53
Voltage Sequence Timing Requirements
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Electrical Specifications Figure 2-24. Voltage Sequence Timing Requirements VID[6:1] / BSEL[2:0] VTT VCCPLL Vcc Tc VCC_BOOT Ta Tb Tg Te PWRGOOD BCLK Tf Td Th Reset Configuration Signals(A[35:3]#, INIT#, SMI#) Reset Configuration Signals BR[1:0]# RESET# Ta= T43 (VCC_BOOT stable to VID[6:1] / BSEL[2:0] valid) Tb= T44 (VID[6:1] / BSEL[2:0] valid to Vcc stable) Tc= T48 (VTT stable to VID[6:1] / BSEL[2:0] valid) Td= T36 (PWRGOOD assertion to RESET# de-assertion) Te= T41 (VCC stable to PWRGOOD assertion) Tf = T37 (BCLK stable to PWRGOOD assertion) Tg = T49 (VCCPLL stable to PWRGOOD assertion) Th = T45 Reset Configuration Signals (A[35:3]#, BR[1:0]#, INIT#, SMI#) Setup Time Ti= T46 Reset Configuration Signals (A[35:3]#, INIT#, SMI#) Hold Time Tj= T47 Reset Configuration Signals (BR[1:0]#) Hold Time Ti Tj Document Number: 318080-002 53