Intel BFCBASE Data Sheet - Page 44

Table 2-25., VID Signal Group AC Specifications, from 0.9 * SM_VCC to V

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Electrical Specifications Table 2-25. VID Signal Group AC Specifications T # Parameter T80: VID Step Time T81: VID Dwell Time at 266.666 MHz FSB T82: VID Down Transition to Valid VCC (min) T83: VID Up Transition to Valid VCC (min) T84: VID Down Transition to Valid VCC (max) T85: VID Up Transition to Valid VCC (max) Min 5 500 Max 0 50 50 0 Unit µs µs µs µs µs µs Figure Notes1, 2 2-27 2-27 2-26,2-27 2-26,2-27 2-26,2-27 2-26,2-27 Notes: 1. See Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design Guidelines for addition information. 2. Platform support for VID transitions is required for the processor to operate within specifications. Table 2-26. SMBus Signal Group AC Specifications T# Parameter Min Max Unit Figure Notes 1, 2 T90: SM_CLK Frequency 10 100 T91: SM_CLK Period 10 100 T92: SM_CLK High Time 4.0 N/A T93: SM_CLK Low Time 4.7 N/A T94: SMBus Rise Time 0.02 1.0 T95: SMBus Fall Time 0.02 0.3 T96: SMBus Output Valid Delay 0.1 4.5 T97: SMBus Input Setup Time 250 N/A T98: SMBus Input Hold Time 300 N/A T99: Bus Free Time 4.7 N/A T100: Hold Time after Repeated Start Condition 4.0 N/A T101: Repeated Start Condition Setup Time 4.7 N/A T102: Stop Condition Setup Time 4.0 N/A KHz µs µs 2-22 µs 2-22 µs 2-22 µs 2-22 µs 2-23 ns 2-22 ns 2-22 µs 2-22 µs 2-22 µs 2-22 µs 2-22 3 3 4, 5 Notes: 1. These parameters are based on design characterization and are not tested. 2. All AC timings for the SMBus signals are referenced at VIL_MAX or VIL_MIN and measured at the processor pins. Refer to Figure 2-23. 3. Rise time is measured from (VIL_MAX - 0.15V) to (VIH_MIN + 0.15V). Fall time is measured from (0.9 * SM_VCC) to (VIL_MAX - 0.15V). DC parameters are specified in Table 2-26. 4. Minimum time allowed between request cycles. 5. Following a write transaction, an internal write cycle time of 10ms must be allowed before starting the next transaction. 44 Document Number: 318080-002

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Electrical Specifications
44
Document Number: 318080-002
Notes:
1.
See
Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design
Guidelines
for addition information.
2.
Platform support for VID transitions is required for the processor to operate within specifications.
Notes:
1.
These parameters are based on design characterization and are not tested.
2.
All AC timings for the SMBus signals are referenced at V
IL_MAX
or V
IL_MIN
and measured at the
processor pins. Refer to
Figure 2-23
.
3.
Rise time is measured from (V
IL_MAX
- 0.15V) to (V
IH_MIN
+ 0.15V). Fall time is measured
from (0.9 * SM_VCC) to (V
IL_MAX
- 0.15V). DC parameters are specified in
Table 2-26
.
4.
Minimum time allowed between request cycles.
5.
Following a write transaction, an internal write cycle time of 10ms must be allowed before
starting the next transaction.
Table 2-25.
VID Signal Group AC Specifications
T # Parameter
Min
Max
Unit
Figure
Notes
1, 2
T80: VID Step Time
5
μs
2-27
T81: VID Dwell Time at 266.666 MHz FSB
500
μs
2-27
T82: VID Down Transition to Valid V
CC
(min)
0
μs
2-26
,
2-27
T83: VID Up Transition to Valid V
CC
(min)
50
μs
2-26
,
2-27
T84: VID Down Transition to Valid V
CC
(max)
50
μs
2-26
,
2-27
T85: VID Up Transition to Valid V
CC
(max)
0
μs
2-26
,
2-27
Table 2-26.
SMBus Signal Group AC Specifications
T# Parameter
Min
Max
Unit
Figure
Notes 1, 2
T90: SM_CLK Frequency
10
100
KHz
T91: SM_CLK Period
10
100
μs
T92: SM_CLK High Time
4.0
N/A
μs
2-22
T93: SM_CLK Low Time
4.7
N/A
μs
2-22
T94: SMBus Rise Time
0.02
1.0
μs
2-22
3
T95: SMBus Fall Time
0.02
0.3
μs
2-22
3
T96: SMBus Output Valid Delay
0.1
4.5
μs
2-23
T97: SMBus Input Setup Time
250
N/A
ns
2-22
T98: SMBus Input Hold Time
300
N/A
ns
2-22
T99: Bus Free Time
4.7
N/A
μs
2-22
4, 5
T100: Hold Time after Repeated Start Condition
4.0
N/A
μs
2-22
T101: Repeated Start Condition Setup Time
4.7
N/A
μs
2-22
T102: Stop Condition Setup Time
4.0
N/A
μs
2-22