Intel BFCBASE Data Sheet - Page 50
FSB Source Synchronous 4X Data Timing Waveform
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Electrical Specifications Figure 2-18. FSB Source Synchronous 4X (Data) Timing Waveform T0 BCLK1 Tp/4 Tp/2 3Tp/4 T1 BCLK0 TD DSTBp# (@ driver) DSTBn# (@ driver) D# (@ driver) TA TB TA TB DSTBp# (@ receiver) TJ DSTBn# (@ receiver) D# (@ receiver) TE TG TE TG TP = T1: BCLK[1:0] Period TA = T21: Source Sync. Data Output Valid Delay Before Data Strobe TB = T22: Source Sync. Data Output Valid Delay After Data Strobe TC = T28: Source Sync. Data Strobe Setup Time to BCLK TD = T30: Data Strobe 'n' (DSTBN#) Output Valid Delay TE = T25: Source Sync. Input Setup Time TG = T26: Source Sync. Input Hold Time TJ = T20: Source Sync. Data Output Valid Delay T2 TC 50 Document Number: 318080-002
Electrical Specifications
50
Document Number: 318080-002
Figure 2-18. FSB Source Synchronous 4X (Data) Timing Waveform
BCLK0
BCLK1
T
p
/4
T
p
/2
3T
p
/4
DSTBp# (@ driver)
D# (@ driver)
D# (@ receiver)
T
J
DSTBn# (@ driver)
DSTBp# (@ receiver)
DSTBn# (@ receiver)
T
E
T
G
T
E
T
G
T
A
T
B
T
A
T
B
T
D
T
C
T
A
= T21: Source Sync. Data Output Valid Delay Before Data Strobe
T
B
= T22: Source Sync. Data Output Valid Delay After Data Strobe
T
C
= T28: Source Sync. Data Strobe Setup Time to BCLK
T
D
= T30: Data Strobe ānā (DSTBN#) Output Valid Delay
T
E
= T25: Source Sync. Input Setup Time
T
G
= T26: Source Sync. Input Hold Time
T
J
= T20: Source Sync. Data Output Valid Delay
T
P
= T1: BCLK[1:0] Period
T0
T1
T2