Intel BFCBASE Data Sheet - Page 27

Document Number: 318080-002

27

Electrical Specifications

9.

Minimum VCC and maximum ICC are specified at the maximum processor case temperature (TCASE)

shown in

Figure 6-2

.

10.

This specification refers to the total reduction of the load line due to VID transitions below the specified

VID.

11.

Individual processor VID values may be calibrated during manufacturing such that two devices at the same

frequency may have different VID settings.

12.

This specification applies to the VCCPLL pin.

13.

Baseboard bandwidth is limited to 20 MHz.

14.

I

CC_TDC

is the sustained (DC equivalent) current that the processor is capable of drawing indefinitely and

should be used for the voltage regulator temperature assessment. The voltage regulator is responsible for

monitoring its temperature and asserting the necessary signal to inform the processor of a thermal

excursion. Please see the applicable design guidelines for further details. The processor is capable of

drawing I

CC_TDC

indefinitely. Refer to

Figure 2-9

for further details on the average processor current draw

over various time durations. This parameter is based on design characterization and is not tested.

15.

This is the maximum total current drawn from the V

TT

plane by only one processor with R

TT

enabled. This

specification does not include the current coming from on-board termination (R

TT

), through the signal line.

Refer to the appropriate platform design guide and the Voltage Regulator Design Guidelines to determine

the total I

TT

drawn by the system. This parameter is based on design characterization and is not tested.

16.

I

CC

_

VTT

_

OUT

is specified at 1.2 V.

17.

I

CC_RESET

is specified while PWRGOOD and RESET# are asserted. Refer to

Table 2-22

for the PWRGOOD to

RESET# de-assertion time specification and

Table 2-23

for the RESET# Pulse Width specification.

Notes:

1.

Processor or Voltage Regulator thermal protection circuitry should not trip for load currents greater than

I

CC_TDC

.

2.

Not 100% tested. Specified by design characterization.

Figure 2-1.

Quad-Core Intel® Xeon® L7345 Processor

Load Current versus Time

40

45

50

55

60

65

0.01

0.1

1

10

100

1000

Time Duration (s)

Sustained Current (A)

Section	Page
1 Introduction	9
1.1 Terminology	11
1.2 State of Data	13
1.3 References	13
2 Electrical Specifications	15
2.1 Front Side Bus and GTLREF	15
2.2 Decoupling Guidelines	15
2.2.1 VCC Decoupling	16
2.2.2 VTT Decoupling	16
2.2.3 Front Side Bus AGTL+ Decoupling	16
2.3 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	16
2.3.1 Front Side Bus Frequency Select Signals (BSEL[2:0])	17
2.3.2 PLL Power Supply	17
2.4 Voltage Identification (VID)	17
2.5 Reserved, Unused, or Test Signals	20
2.6 Front Side Bus Signal Groups	20
2.7 CMOS Asynchronous and Open Drain Asynchronous Signals	22
2.8 Test Access Port (TAP) Connection	22
2.9 Mixing Processors	23
2.10 Absolute Maximum and Minimum Ratings	23
2.11 Processor DC Specifications	24
2.11.1 Flexible Motherboard Guidelines (FMB)	25
2.11.2 Platform Environmental Control Interface (PECI) DC Specifications	35
2.11.3 VCC Overshoot Specification	37
2.11.4 AGTL+ FSB Specifications	38
2.12 Front Side Bus AC Specifications	40
2.13 Processor AC Timing Waveforms	45
3 Mechanical Specifications	57
3.1 Package Mechanical Drawing	57
3.2 Processor Component Keepout Zones	60
3.3 Package Loading Specifications	66
3.4 Package Handling Guidelines	67
3.5 Package Insertion Specifications	67
3.6 Processor Mass Specifications	67
3.7 Processor Materials	67
3.8 Processor Markings	68
3.9 Processor Pin-Out Coordinates	69
4 Pin Listing	71
4.1 Pin Assignments	71
4.1.1 Pin Listing by Pin Name	71
4.1.2 Pin Listing by Pin Number	79
5 Signal Definitions	87
5.1 Signal Definitions.	87
6 Thermal Specifications	95
6.1 Package Thermal Specifications	95
6.1.1 Thermal Specifications	95
6.1.2 Thermal Metrology	102
6.2 Processor Thermal Features	103
6.2.1 Thermal Monitor Features	103
6.2.2 Thermal Monitor	103
6.2.3 Thermal Monitor 2	104
6.2.4 On-Demand Mode	105
6.2.5 PROCHOT# Signal	106
6.2.6 FORCEPR# Signal	106
6.2.7 THERMTRIP# Signal	106
6.3 Platform Environment Control Interface (PECI)	107
6.3.1 Introduction	107
6.3.2 PECI Specifications	108
7 Features	111
7.1 Power-On Configuration Options	111
7.2 Clock Control and Low Power States	111
7.2.1 Normal State	112
7.2.2 HALT or Extended HALT State	112
7.2.3 Stop-Grant State	114
7.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State	115
7.3 Enhanced Intel SpeedStep® Technology	115
7.4 System Management Bus (SMBus) Interface	116
7.4.1 SMBus Device Addressing	117
7.4.2 PIROM and Scratch EEPROM Supported SMBus Transactions	118
7.4.3 Processor Information ROM (PIROM)	119
7.4.4 Checksums	137
7.4.5 Scratch EEPROM	137
8 Boxed Processor Specifications	139
8.1 Introduction	139
8.2 Thermal Specifications	139
8.2.1 Boxed Processor Cooling Requirements	139
9 Debug Tools Specifications	141
9.1 Debug Port System Requirements	141
9.2 Logic Analyzer Interface (LAI)	141
9.2.1 Mechanical Considerations	141

Intel BFCBASE Data Sheet - Page 27

Quad-Core Intel® Xeon® L7345 Processor, Load Current versus Time, Time Duration s

Page 27 highlights