Intel BFCBASE Data Sheet - Page 71

Document Number: 318080-002

71

Pin Listing

4

Pin Listing

4.1

Pin Assignments

Section 2.6

contains the front side bus signal groups for the Intel

®

Xeon

®

Processor

7200 Series and 7300 Series (see

Table 2-4

). This section provides a sorted pin lists in

Table 4-1

and

Table 4-2

.

Table 4-1

is a listing of all processor pins ordered alphabetically by pin name.

Table 4-2

is a listing of all processor pins ordered by pin number.

4.1.1

Pin Listing by Pin Name

Table 4-1. Pin Listing by Pin Name (Sheet 1

of 16)

Pin Name

Pin No.

Signal

Buffer Type

Direction

A3#

A22

Source Sync

Input/Output

A4#

A20

Source Sync

Input/Output

A5#

B18

Source Sync

Input/Output

A6#

C18

Source Sync

Input/Output

A7#

A19

Source Sync

Input/Output

A8#

C17

Source Sync

Input/Output

A9#

D17

Source Sync

Input/Output

A10#

A13

Source Sync

Input/Output

A11#

B16

Source Sync

Input/Output

A12#

B14

Source Sync

Input/Output

A13#

B13

Source Sync

Input/Output

A14#

A12

Source Sync

Input/Output

A15#

C15

Source Sync

Input/Output

A16#

C14

Source Sync

Input/Output

A17#

D16

Source Sync

Input/Output

A18#

D15

Source Sync

Input/Output

A19#

F15

Source Sync

Input/Output

A20#

A10

Source Sync

Input/Output

A21#

B10

Source Sync

Input/Output

A22#

B11

Source Sync

Input/Output

A23#

C12

Source Sync

Input/Output

A24#

E14

Source Sync

Input/Output

A25#

D13

Source Sync

Input/Output

A26#

A9

Source Sync

Input/Output

A27#

B8

Source Sync

Input/Output

A28#

E13

Source Sync

Input/Output

A29#

D12

Source Sync

Input/Output

A30#

C11

Source Sync

Input/Output

A31#

B7

Source Sync

Input/Output

A32#

A6

Source Sync

Input/Output

A33#

A7

Source Sync

Input/Output

A34#

C9

Source Sync

Input/Output

A35#

C8

Source Sync

Input/Output

A36#

F16

Source Sync

Input/Output

A37#

F22

Source Sync

Input/Output

A38#

B6

Source Sync

Input/Output

A39#

C16

Source Sync

Input/Output

A20M#

F27

Async GTL+

Input

ADS#

D19

Common Clk

Input/Output

ADSTB0#

F17

Source Sync

Input/Output

ADSTB1#

F14

Source Sync

Input/Output

AP0#

E10

Common Clk

Input/Output

AP1#

D9

Common Clk

Input/Output

BCLK0

Y4

FSB Clk

Input

BCLK1

W5

FSB Clk

Input

BINIT#

F11

Common Clk

Input/Output

BNR#

F20

Common Clk

Input/Output

BPM0#

F6

Common Clk

Input/Output

BPM1#

F8

Common Clk

Output

BPM2#

E7

Common Clk

Output

BPM3#

F5

Common Clk

Input/Output

BPM4#

E8

Common Clk

Output

BPM5#

E4

Common Clk

Input/Output

BPMb0#

AA4

Common Clk

Input/Output

BPMb1#

AC1

Common Clk

Output

BPMb2#

AE2

Common Clk

Output

Table 4-1. Pin Listing by Pin Name (Sheet 2

of 16)

Pin Name

Pin No.

Signal

Buffer Type

Direction

Section	Page
1 Introduction	9
1.1 Terminology	11
1.2 State of Data	13
1.3 References	13
2 Electrical Specifications	15
2.1 Front Side Bus and GTLREF	15
2.2 Decoupling Guidelines	15
2.2.1 VCC Decoupling	16
2.2.2 VTT Decoupling	16
2.2.3 Front Side Bus AGTL+ Decoupling	16
2.3 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	16
2.3.1 Front Side Bus Frequency Select Signals (BSEL[2:0])	17
2.3.2 PLL Power Supply	17
2.4 Voltage Identification (VID)	17
2.5 Reserved, Unused, or Test Signals	20
2.6 Front Side Bus Signal Groups	20
2.7 CMOS Asynchronous and Open Drain Asynchronous Signals	22
2.8 Test Access Port (TAP) Connection	22
2.9 Mixing Processors	23
2.10 Absolute Maximum and Minimum Ratings	23
2.11 Processor DC Specifications	24
2.11.1 Flexible Motherboard Guidelines (FMB)	25
2.11.2 Platform Environmental Control Interface (PECI) DC Specifications	35
2.11.3 VCC Overshoot Specification	37
2.11.4 AGTL+ FSB Specifications	38
2.12 Front Side Bus AC Specifications	40
2.13 Processor AC Timing Waveforms	45
3 Mechanical Specifications	57
3.1 Package Mechanical Drawing	57
3.2 Processor Component Keepout Zones	60
3.3 Package Loading Specifications	66
3.4 Package Handling Guidelines	67
3.5 Package Insertion Specifications	67
3.6 Processor Mass Specifications	67
3.7 Processor Materials	67
3.8 Processor Markings	68
3.9 Processor Pin-Out Coordinates	69
4 Pin Listing	71
4.1 Pin Assignments	71
4.1.1 Pin Listing by Pin Name	71
4.1.2 Pin Listing by Pin Number	79
5 Signal Definitions	87
5.1 Signal Definitions.	87
6 Thermal Specifications	95
6.1 Package Thermal Specifications	95
6.1.1 Thermal Specifications	95
6.1.2 Thermal Metrology	102
6.2 Processor Thermal Features	103
6.2.1 Thermal Monitor Features	103
6.2.2 Thermal Monitor	103
6.2.3 Thermal Monitor 2	104
6.2.4 On-Demand Mode	105
6.2.5 PROCHOT# Signal	106
6.2.6 FORCEPR# Signal	106
6.2.7 THERMTRIP# Signal	106
6.3 Platform Environment Control Interface (PECI)	107
6.3.1 Introduction	107
6.3.2 PECI Specifications	108
7 Features	111
7.1 Power-On Configuration Options	111
7.2 Clock Control and Low Power States	111
7.2.1 Normal State	112
7.2.2 HALT or Extended HALT State	112
7.2.3 Stop-Grant State	114
7.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State	115
7.3 Enhanced Intel SpeedStep® Technology	115
7.4 System Management Bus (SMBus) Interface	116
7.4.1 SMBus Device Addressing	117
7.4.2 PIROM and Scratch EEPROM Supported SMBus Transactions	118
7.4.3 Processor Information ROM (PIROM)	119
7.4.4 Checksums	137
7.4.5 Scratch EEPROM	137
8 Boxed Processor Specifications	139
8.1 Introduction	139
8.2 Thermal Specifications	139
8.2.1 Boxed Processor Cooling Requirements	139
9 Debug Tools Specifications	141
9.1 Debug Port System Requirements	141
9.2 Logic Analyzer Interface (LAI)	141
9.2.1 Mechanical Considerations	141

Intel BFCBASE Data Sheet - Page 71

Pin Listing, 4.1 Pin Assignments, 4.1.1 Pin Listing by Pin Name

Page 71 highlights