Intel BFCBASE Data Sheet - Page 114

Features Figure 7-1. Stop Clock State Machine Normal State Normal execution HALT or MWAIT Instruction and HALT Bus Cycle Generated INIT#, BINIT#, INTR, NMI, SMI#, RESET#, FSB interrupts Extended HALT or HALT State BCLK running Snoops and interrupts allowed STPCLK# Asserted STPCLK# De-asserted Stop Grant State BCLK running Snoops and interrupts allowed STAPsCsLeKrt#eSdTDPeC-LaKss#erted Snoop Event Occurs Snoop Event Serviced Snoop Snoop Event Event Occurs Serviced Extended HALT Snoop or HALT Snoop State BCLK running Service snoops to caches Stop Grant Snoop State BCLK running Service snoops to caches 7.2.3 Stop-Grant State When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20 bus clocks after the response phase of the processor issued Stop Grant Acknowledge special bus cycle. Once the STPCLK# pin has been asserted, it may only be deasserted once the processor is in the Stop Grant state. All processor cores will enter the StopGrant state once the STPCLK# pin is asserted. Additionally, all processor cores must be in the Stop Grant state before the deassertion of STPCLK#. Since the AGTL+ signal pins receive power from the front side bus, these pins should not be driven (allowing the level to return to VTT) for minimum power drawn by the termination resistors in this state. In addition, all other input pins on the front side bus should be driven to the inactive state. BINIT# will not be serviced while the processor is in Stop-Grant state. The event will be latched and can be serviced by software upon exit from the Stop Grant state. RESET# will cause the processor to immediately initialize itself, but the processor will stay in Stop-Grant state. A transition back to the Normal state will occur with the deassertion of the STPCLK# signal. A transition to the Grant Snoop state will occur when the processor detects a snoop on the front side bus (see Section 7.2.4.1). 114 Document Number: 318080-002