Intel BFCBASE Data Sheet - Page 90

Signal Definitions

90

Document Number: 318080-002

DSTBN[3:0]#

I/O

Data strobe used to latch in D[63:0]#.

DSTBP[3:0]#

I/O

Data strobe used to latch in D[63:0]#.

FERR#/PBE#

O

FERR#/PBE# (floating-point error/pending break event) is a multiplexed signal and

its meaning is qualified by STPCLK#. When STPCLK# is not asserted, FERR#/PBE#

indicates a floating-point error and will be asserted when the processor detects an

unmasked floating-point error. When STPCLK# is not asserted, FERR#/PBE# is

similar to the ERROR# signal on the Intel 387 coprocessor, and is included for

compatibility with systems using MS-DOS*-type floating-point error reporting. When

STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the processor has a

pending break event waiting for service. The assertion of FERR#/PBE# indicates that

the processor should be returned to the Normal state. For additional information on

the pending break event functionality, including the identification of support of the

feature and enable/disable information, refer to Vol. 3 of the

IA_32 Intel ®

Architecture Software Developer’s Manual

and the

AP-485 Intel® Processor

Identification and the CPUID Instruction

application note.

FORCEPR#

I

The FORCEPR# (force power reduction) input can be used by the platform to cause

the Intel

®

Xeon

®

Processor 7200 Series and 7300 Series to activate the Thermal

Control Circuit (TCC).

GTLREF_ADD_MID

GTLREF_ADD_END

I

GTLREF_ADD determines the signal reference level for AGTL+ address and common

clock input pins. GTLREF_ADD is used by the AGTL+ receivers to determine if a signal

is a logical 0 or a logical 1. Please refer to

Table 2-17

and the appropriate platform

design guidelines for additional details.

GTLREF_DATA_MID

GTLREF_DATA_END

I

GTLREF_DATA determines the signal reference level for AGTL+ data input pins.

GTLREF_DATA is used by the AGTL+ receivers to determine if a signal is a logical 0 or

a logical 1. Please refer to

Table 2-17

and the appropriate platform design guidelines

for additional details.

HIT#

HITM#

I/O

I/O

HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation

results. Any FSB agent may assert both HIT# and HITM# together to indicate that it

requires a snoop stall, which can be continued by reasserting HIT# and HITM#

together.

IERR#

O

IERR# (Internal Error) is asserted by a processor as the result of an internal error.

Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the

processor FSB. This transaction may optionally be converted to an external error

signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted until

the assertion of RESET#.

This signal does not have on-die termination.

Table 5-1.

Signal Definitions (Sheet 4 of 8)

Name

Type

Description

Notes

Signals

Associated Strobes

D[15:0]#, DBI0#

DSTBN0#

D[31:16]#, DBI1#

DSTBN1#

D[47:32]#, DBI2#

DSTBN2#

D[63:48]#, DBI3#

DSTBN3#

Signals

Associated Strobes

D[15:0]#, DBI0#

DSTBP0#

D[31:16]#, DBI1#

DSTBP1#

D[47:32]#, DBI2#

DSTBP2#

D[63:48]#, DBI3#

DSTBP3#

Section	Page
1 Introduction	9
1.1 Terminology	11
1.2 State of Data	13
1.3 References	13
2 Electrical Specifications	15
2.1 Front Side Bus and GTLREF	15
2.2 Decoupling Guidelines	15
2.2.1 VCC Decoupling	16
2.2.2 VTT Decoupling	16
2.2.3 Front Side Bus AGTL+ Decoupling	16
2.3 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	16
2.3.1 Front Side Bus Frequency Select Signals (BSEL[2:0])	17
2.3.2 PLL Power Supply	17
2.4 Voltage Identification (VID)	17
2.5 Reserved, Unused, or Test Signals	20
2.6 Front Side Bus Signal Groups	20
2.7 CMOS Asynchronous and Open Drain Asynchronous Signals	22
2.8 Test Access Port (TAP) Connection	22
2.9 Mixing Processors	23
2.10 Absolute Maximum and Minimum Ratings	23
2.11 Processor DC Specifications	24
2.11.1 Flexible Motherboard Guidelines (FMB)	25
2.11.2 Platform Environmental Control Interface (PECI) DC Specifications	35
2.11.3 VCC Overshoot Specification	37
2.11.4 AGTL+ FSB Specifications	38
2.12 Front Side Bus AC Specifications	40
2.13 Processor AC Timing Waveforms	45
3 Mechanical Specifications	57
3.1 Package Mechanical Drawing	57
3.2 Processor Component Keepout Zones	60
3.3 Package Loading Specifications	66
3.4 Package Handling Guidelines	67
3.5 Package Insertion Specifications	67
3.6 Processor Mass Specifications	67
3.7 Processor Materials	67
3.8 Processor Markings	68
3.9 Processor Pin-Out Coordinates	69
4 Pin Listing	71
4.1 Pin Assignments	71
4.1.1 Pin Listing by Pin Name	71
4.1.2 Pin Listing by Pin Number	79
5 Signal Definitions	87
5.1 Signal Definitions.	87
6 Thermal Specifications	95
6.1 Package Thermal Specifications	95
6.1.1 Thermal Specifications	95
6.1.2 Thermal Metrology	102
6.2 Processor Thermal Features	103
6.2.1 Thermal Monitor Features	103
6.2.2 Thermal Monitor	103
6.2.3 Thermal Monitor 2	104
6.2.4 On-Demand Mode	105
6.2.5 PROCHOT# Signal	106
6.2.6 FORCEPR# Signal	106
6.2.7 THERMTRIP# Signal	106
6.3 Platform Environment Control Interface (PECI)	107
6.3.1 Introduction	107
6.3.2 PECI Specifications	108
7 Features	111
7.1 Power-On Configuration Options	111
7.2 Clock Control and Low Power States	111
7.2.1 Normal State	112
7.2.2 HALT or Extended HALT State	112
7.2.3 Stop-Grant State	114
7.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State	115
7.3 Enhanced Intel SpeedStep® Technology	115
7.4 System Management Bus (SMBus) Interface	116
7.4.1 SMBus Device Addressing	117
7.4.2 PIROM and Scratch EEPROM Supported SMBus Transactions	118
7.4.3 Processor Information ROM (PIROM)	119
7.4.4 Checksums	137
7.4.5 Scratch EEPROM	137
8 Boxed Processor Specifications	139
8.1 Introduction	139
8.2 Thermal Specifications	139
8.2.1 Boxed Processor Cooling Requirements	139
9 Debug Tools Specifications	141
9.1 Debug Port System Requirements	141
9.2 Logic Analyzer Interface (LAI)	141
9.2.1 Mechanical Considerations	141

Intel BFCBASE Data Sheet - Page 90

Table 5-1., Signal Definitions Sheet 4 of 8, Description, Notes, Signals, Associated Strobes

Page 90 highlights