Intel BFCBASE Data Sheet - Page 116
System Management Bus (SMBus) Interface, unconnected SM_CLK, SM_DAT, SM_EP_A[2:0], SM_WP.
UPC - 735858197373
View all Intel BFCBASE manuals
Add to My Manuals
Save this manual to your list of manuals |
Page 116 highlights
7.4 Note: Features Enhanced Intel SpeedStep Technology creates processor performance states (P-states) or voltage/frequency operating points. P-states are lower power capability states within the Normal state as shown in Figure 7-1. Enhanced Intel SpeedStep Technology enables real-time dynamic switching between frequency and voltage points. It alters the performance of the processor by changing the bus to core frequency ratio and voltage. This allows the processor to run at different core frequencies and voltages to best serve the performance and power requirements of the processor and system. The Intel® Xeon® Processor 7200 Series and 7300 Series have hardware logic that coordinates the requested voltage (VID) between the processor cores. The highest voltage requested from the four processor cores is selected for that processor package. Note that the front side bus is not altered; only the internal core frequency is changed. In order to run at reduced power consumption, the voltage is altered in step with the bus ratio. The following are key features of Enhanced Intel SpeedStep Technology: • Multiple voltage/frequency operating points provide optimal performance at reduced power consumption. • Voltage/frequency selection is software controlled by writing to processor MSR's (Model Specific Registers), thus eliminating chipset dependency. - If the target frequency is higher than the current frequency, VCC is incremented in steps (+12.5 mV) by placing a new value on the VID signals and the processor shifts to the new frequency. Note that the top frequency for the processor can not be exceeded. - If the target frequency is lower than the current frequency, the processor shifts to the new frequency and VCC is then decremented in steps (-12.5 mV) by changing the target VID through the VID signals. System Management Bus (SMBus) Interface The Intel® Xeon® Processor 7200 Series and 7300 Series package includes an SMBus interface which allows access to a memory component with two sections (referred to as the Processor Information ROM and the Scratch EEPROM). These devices and their features are described below. The SMBus on-package thermal sensor has been removed and is no longer used. Refer to Section 6.3 for details about the new digital thermometer and PECI interface. The processor SMBus implementation uses the clock and data signals of the System Management Bus (SMBus) Specification. It does not implement the SMBSUS# signal. For platforms which do not implement any of the SMBus features found on the processor, all of the SMBus connections, except SM_VCC, to the socket pins may be left unconnected (SM_CLK, SM_DAT, SM_EP_A[2:0], SM_WP). 116 Document Number: 318080-002