Intel BFCBASE Data Sheet - Page 40

Electrical Specifications 2.12 Front Side Bus AC Specifications The processor FSB timings specified in this section are defined at the processor core (pads). Therefore, proper simulation of the FSB is the only means to verify proper timing and signal quality. See Table 4-1 for the pin listing and Table 5-1 for signal definitions. Table 2-19 through Table 2-24 list the AC specifications associated with the processor FSB. All AGTL+ timings are referenced to GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END for both '0' and '1' logic levels unless otherwise specified. The timings specified in this section should be used in conjunction with the processor signal integrity models provided by Intel. AGTL+ layout guidelines are also available in the appropriate platform design guidelines. Note: Care should be taken to read all notes associated with a particular timing parameter. Table 2-19. Front Side Bus Differential Clock AC Specifications T# Parameter FSB Clock Frequency T1: BCLK[1:0] Period T2: BCLK[1:0] Period Stability T3: BCLK[1:0] Rise Time T4: BCLK[1:0] Fall Time Differential Rising and Falling Edge Rates Min 265.247 3.7489 N/A 175 175 0.6 Max 266.745 3.7700 150 700 700 4 Unit MHz ns ps ps ps V/ns Figure 2-13 Notes1 2 3 4 5 5 7 Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. The processor core clock frequency is derived from BCLK. The bus clock to processor core clock ratio is determined during initialization as described in Section 2.3. Table 2-1 includes core frequency to FSB multipliers. 3. The period specified here is the average period. A given period may vary from this specification as governed by the period stability specification (T2). 4. In this context, period stability is defined as the worst case timing difference between successive crossover voltages. In other words, the largest absolute difference between adjacent clock periods must be less than the period stability. 5. Rise and fall times are measured single ended between 245 mV and 455 mV of the clock swing. 6. Measured from -200 mV to +200 mV. The signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is centered on the differential zero. Table 2-20. Front Side Bus Common Clock AC Specifications T# Parameter T10: Common Clock Output Valid Delay T11: Common Clock Input Setup Time T12: Common Clock Input Hold Time T13: RESET# Pulse Width Min 0.22 0.650 0.150 1 Max 1.10 N/A N/A 10 Unit ns ns ns ms Figure 2-16 2-16 2-16 2-24 Notes1, 2, 3 4 5 5 6, 7, 8 Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Not 100% tested. Specified by design characterization. 3. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage (VCROSS) of the BCLK[1:0] at rising edge of BCLK0. All common clock AGTL+ signal timings are referenced at nominal GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END at the processor core (pads). 4. Valid delay timings for these signals are specified into the test circuit described in Figure 2-11 and with GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END at 0.67 * VTT. 40 Document Number: 318080-002