Intel BFCBASE Data Sheet - Page 26

Electrical Specifications

26

Document Number: 318080-002

Notes:

1.

Unless otherwise noted, all specifications in this table apply to all processors and are based on estimates

and simulations, not empirical data. These specifications will be updated with characterized data from

silicon measurements at a later date.

2.

These voltages are targets only. A variable voltage source should exist on systems in the event that a

different voltage is required. See

Section 2.4

for more information.

3.

The voltage specification requirements are measured across the VCC_SENSE and VSS_SENSE pins and

across the VCC_SENSE2 and VSS_SENSE2 pins with an oscilloscope set to 100 MHz bandwidth, 1.5 pF

maximum probe capacitance, and 1 M

Ω

minimum impedance. The maximum length of ground wire on the

probe should be less than 5 mm. Ensure external noise from the system is not coupled in the scope probe.

4.

The processor must not be subjected to any static V

CC

level that exceeds the V

CC_MAX

associated with any

particular current. Failure to adhere to this specification can shorten processor lifetime.

5.

I

CC_MAX

specification is based on maximum V

CC

loadline Refer to

Figure 2-10

for details. The processor is

capable of drawing I

CC_MAX

for up to 10 ms. Refer to

Figure 2-9

for further details on the average processor

current draw over various time durations.

6.

FMB is the flexible motherboard guideline. These guidelines are for estimation purposes only. See

Section 2.11.1

for further details on FMB guidelines.

7.

This specification represents the total current for GTLREF_DATA_MID, GTLREF_DATA_END,

GTLREF_ADD_MID, and GTLREF_ADD_END.

8.

V

TT

must be provided via a separate voltage source and must not be connected to V

CC

. This specification is

measured at the pin.

I

TT

I

CC

for V

TT

supply before V

CC

stable

I

CC

for V

TT

supply after V

CC

stable

8.0

7.0

A

15

I

CC_TDC

Thermal Design Current (TDC) Quad-

Core Intel® Xeon® L7345 Processor

Launch - FMB

50

A

6,14

I

CC_TDC

Thermal Design Current (TDC) Dual-

Core Intel® Xeon® Processor 7200

Series

Launch - FMB

75

A

6,14

I

CC_TDC

Thermal Design Current (TDC) Intel

®

Xeon

®

Processor 7200 Series and 7300

Series

Launch - FMB

75

A

6,14

I

CC_TDC

Thermal Design Current (TDC) Intel®

Xeon® X7350 Processor

Launch - FMB

110

A

6,14

I

CC_VTT_OUT

DC current that may be drawn from

V

TT_OUT

per pin

580

mA

16

I

CC_GTLREF

I

CC

for

GTLREF_DATA_MID,

GTLREF_DATA_END,

GTLREF_ADD_MID, and

GTLREF_ADD_END

200

μA

7

I

CC_VCCPLL

I

CC

for PLL supply

260

mA

12

I

TCC

I

CC

for Quad-Core Intel® Xeon® L7345

Processor during active thermal control

circuit (TCC)

60

A

I

TCC

I

CC

for Dual-Core Intel® Xeon®

Processor 7200 Series during active

thermal control circuit (TCC)

90

A

I

TCC

I

CC

for Dual-Core Intel® Xeon®

Processor 7200 Series and Quad-Core

Intel® Xeon® Processor 7300 Series

during active thermal control circuit

(TCC)

90

A

I

TCC

I

CC

for Intel® Xeon® X7350 Processor

during active thermal control circuit

(TCC)

130

A

Table 2-9.

Voltage and Current Specifications

(Sheet 2 of 2)

Symbol

Parameter

Min

Typ

Max

Unit

Notes

1,17

Section	Page
1 Introduction	9
1.1 Terminology	11
1.2 State of Data	13
1.3 References	13
2 Electrical Specifications	15
2.1 Front Side Bus and GTLREF	15
2.2 Decoupling Guidelines	15
2.2.1 VCC Decoupling	16
2.2.2 VTT Decoupling	16
2.2.3 Front Side Bus AGTL+ Decoupling	16
2.3 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	16
2.3.1 Front Side Bus Frequency Select Signals (BSEL[2:0])	17
2.3.2 PLL Power Supply	17
2.4 Voltage Identification (VID)	17
2.5 Reserved, Unused, or Test Signals	20
2.6 Front Side Bus Signal Groups	20
2.7 CMOS Asynchronous and Open Drain Asynchronous Signals	22
2.8 Test Access Port (TAP) Connection	22
2.9 Mixing Processors	23
2.10 Absolute Maximum and Minimum Ratings	23
2.11 Processor DC Specifications	24
2.11.1 Flexible Motherboard Guidelines (FMB)	25
2.11.2 Platform Environmental Control Interface (PECI) DC Specifications	35
2.11.3 VCC Overshoot Specification	37
2.11.4 AGTL+ FSB Specifications	38
2.12 Front Side Bus AC Specifications	40
2.13 Processor AC Timing Waveforms	45
3 Mechanical Specifications	57
3.1 Package Mechanical Drawing	57
3.2 Processor Component Keepout Zones	60
3.3 Package Loading Specifications	66
3.4 Package Handling Guidelines	67
3.5 Package Insertion Specifications	67
3.6 Processor Mass Specifications	67
3.7 Processor Materials	67
3.8 Processor Markings	68
3.9 Processor Pin-Out Coordinates	69
4 Pin Listing	71
4.1 Pin Assignments	71
4.1.1 Pin Listing by Pin Name	71
4.1.2 Pin Listing by Pin Number	79
5 Signal Definitions	87
5.1 Signal Definitions.	87
6 Thermal Specifications	95
6.1 Package Thermal Specifications	95
6.1.1 Thermal Specifications	95
6.1.2 Thermal Metrology	102
6.2 Processor Thermal Features	103
6.2.1 Thermal Monitor Features	103
6.2.2 Thermal Monitor	103
6.2.3 Thermal Monitor 2	104
6.2.4 On-Demand Mode	105
6.2.5 PROCHOT# Signal	106
6.2.6 FORCEPR# Signal	106
6.2.7 THERMTRIP# Signal	106
6.3 Platform Environment Control Interface (PECI)	107
6.3.1 Introduction	107
6.3.2 PECI Specifications	108
7 Features	111
7.1 Power-On Configuration Options	111
7.2 Clock Control and Low Power States	111
7.2.1 Normal State	112
7.2.2 HALT or Extended HALT State	112
7.2.3 Stop-Grant State	114
7.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State	115
7.3 Enhanced Intel SpeedStep® Technology	115
7.4 System Management Bus (SMBus) Interface	116
7.4.1 SMBus Device Addressing	117
7.4.2 PIROM and Scratch EEPROM Supported SMBus Transactions	118
7.4.3 Processor Information ROM (PIROM)	119
7.4.4 Checksums	137
7.4.5 Scratch EEPROM	137
8 Boxed Processor Specifications	139
8.1 Introduction	139
8.2 Thermal Specifications	139
8.2.1 Boxed Processor Cooling Requirements	139
9 Debug Tools Specifications	141
9.1 Debug Port System Requirements	141
9.2 Logic Analyzer Interface (LAI)	141
9.2.1 Mechanical Considerations	141

Intel BFCBASE Data Sheet - Page 26

Table 2-9., Voltage and Current Specifications, Sheet 2 of 2, Symbol, Parameter, Notes

Page 26 highlights