Intel BFCBASE Data Sheet - Page 36

DC Characteristics, Input Device Hysteresis, Table 2-15., PECI DC Electrical Limits

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Electrical Specifications 7300 Series contains Digital Thermal Sensors (DTS) distributed throughout the die. These sensors are implemented as analog-to-digital converters calibrated at the factory for reasonable accuracy to provide a digital representation of relative processor temperature. PECI provides an interface to relay the highest DTS temperature within a die to external management devices for thermal/fan speed control. 2.11.2.1 DC Characteristics A PECI device interface operates at a nominal voltage set by VTT. The set of DC electrical specifications shown in Table 2-15 is used with devices normally operating from a VTT interface supply. VTT nominal levels will vary between processor families. All PECI devices will operate at the VTT level determined by the processor installed in the system. For specific nominal VTT levels, refer to Table 2-11. Table 2-15. PECI DC Electrical Limits Symbol Vin Vhysteresis Vn Vp Isource Isink Ileak+ Ileak- Cbus Vnoise Definition and Conditions Min Input Voltage Range -0.150 Hysteresis Negative-edge threshold voltage Positive-edge threshold voltage High level output source (VOH = 0.75 * VTT) Low level output sink (VOL = 0.25 * VTT) High impedance state leakage to VTT (Vleak = VOL) High impedance leakage to GND (Vleak = VOH) Bus capacitance 0.1 * VTT 0.275 * VTT 0.550 * VTT -6.0 0.5 N/A N/A N/A Signal noise immunity above 300 MHz 0.1 * VTT Max VTT N/A 0.500 * VTT 0.762 * VTT N/A 1.0 50 10 10 N/A Units V V V V mA mA µA µA pF Vp-p Notes1 2 2 3 Note: 1. VTT supplies the PECI interface. PECI behavior does not affect VTT min/max specifications. 2. The leakage specification applies to powered devices on the PECI bus. 3. One node is counted for each client and one node for the system host. Extended trace lengths might appear as additional nodes. 2.11.2.2 Input Device Hysteresis The input buffers in both client and host models must use a Schmitt-triggered input design for improved noise immunity. Use Figure 2-9 as a guide for input buffer design. 36 Document Number: 318080-002

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Electrical Specifications
36
Document Number: 318080-002
7300 Series contains Digital Thermal Sensors (DTS) distributed throughout the die.
These sensors are implemented as analog-to-digital converters calibrated at the factory
for reasonable accuracy to provide a digital representation of relative processor
temperature. PECI provides an interface to relay the highest DTS temperature within a
die to external management devices for thermal/fan speed control.
2.11.2.1
DC Characteristics
A PECI device interface operates at a nominal voltage set by V
TT
. The set of DC
electrical specifications shown in
Table 2-15
is used with devices normally operating
from a V
TT
interface supply. V
TT
nominal levels will vary between processor families. All
PECI devices will operate at the V
TT
level determined by the processor installed in the
system. For specific nominal V
TT
levels, refer to
Table 2-11
.
Note:
1.
V
TT
supplies the PECI interface. PECI behavior does not affect V
TT
min/max specifications.
2.
The leakage specification applies to powered devices on the PECI bus.
3.
One node is counted for each client and one node for the system host. Extended trace lengths might
appear as additional nodes.
2.11.2.2
Input Device Hysteresis
The input buffers in both client and host models must use a Schmitt-triggered input
design for improved noise immunity. Use
Figure 2-9
as a guide for input buffer design.
Table 2-15.
PECI DC Electrical Limits
Symbol
Definition and Conditions
Min
Max
Units
Notes
1
V
in
Input Voltage Range
-0.150
V
TT
V
V
hysteresis
Hysteresis
0.1 * V
TT
N/A
V
V
n
Negative-edge threshold voltage
0.275 * V
TT
0.500 * V
TT
V
V
p
Positive-edge threshold voltage
0.550 * V
TT
0.762 * V
TT
V
I
source
High level output source
(V
OH
= 0.75 * V
TT
)
-6.0
N/A
mA
I
sink
Low level output sink
(V
OL
= 0.25 * V
TT
)
0.5
1.0
mA
I
leak+
High impedance state leakage to V
TT
(V
leak
= V
OL
)
N/A
50
μA
2
I
leak-
High impedance leakage to GND
(V
leak
= V
OH
)
N/A
10
μA
2
C
bus
Bus capacitance
N/A
10
pF
3
V
noise
Signal noise immunity above 300 MHz
0.1 * V
TT
N/A
V
p-p