Intel BFCBASE Data Sheet - Page 137
Checksums, 7.4.5 Scratch EEPROM, Table 7-7., Byte ROM Checksum Values
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Features Offset: 7Fh Bit Description 7:0 Feature Data Checksum One Byte Checksum of the Feature Data Section 00h- FFh: See Section 7.4.4 for calculation of the value 7.4.4 Checksums The PIROM includes multiple checksums. Table 7-7 includes the checksum values for each section defined in the 128 byte ROM. Table 7-7. 128 Byte ROM Checksum Values Section Header Processor Data Processor Core Data Cache Data Package Data Part Number Data Thermal Ref. Data Feature Data Checksum Address 0Dh 15h 24h 31h 37h 6Fh 73h 7Fh Checksums are automatically calculated and programmed by Intel. The first step in calculating the checksum is to add each byte from the field to the next subsequent byte. This result is then negated to provide the checksum. Example: For a byte string of AA445Ch, the resulting checksum will be B6h. AA = 10101010 44 = 01000100 5C = 0101100 AA + 44 + 5C = 01001010 Negate the sum: 10110101 +1 = 101101 (B6h) 7.4.5 Scratch EEPROM Also available in the memory component on the processor SMBus is an EEPROM which may be used for other data at the system or processor vendor's discretion. The data in this EEPROM, once programmed, can be write-protected by asserting the active-high SM_WP signal. This signal has a weak pull-down (10 kΩ) to allow the EEPROM to be programmed in systems with no implementation of this signal. The Scratch EEPROM resides in the upper half of the memory component (addresses 80 - FFh). The lower half comprises the Processor Information ROM (addresses 00 - 7Fh), which is permanently write-protected by Intel. § Document Number: 318080-002 137