Intel BFCBASE Data Sheet - Page 51

TAP Valid Delay Timing Waveform, THERMTRIP# Power Down Sequence

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Electrical Specifications Figure 2-19. TAP Valid Delay Timing Waveform TCK V Tx Ts Th Signal V Valid Tx = T58: TDO Clock to Output Delay Ts = T56: TDI, TMS Setup Time Th = T57: TDI, TMS Hold Time V = 0.5 * VTT Note: Please refer to Table 2-12 for TAP Signal Group DC specifications and Table 2-24 for TAP Signal Group AC specifications. Figure 2-20. Test Reset (TRST#), Async GTL+ Input, and PROCHOT# Timing Waveform V Tq T q = T59 (TRST# Pulse Width), V = 0.5 * VTT T38 (PROCHOT# Pulse Width), V = GTLREF Figure 2-21. THERMTRIP# Power Down Sequence TA THERMTRIP# Vcc VTT TA = T39 (THERMTRIP# to removal of power) Document Number: 318080-002 51

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Document Number: 318080-002
51
Electrical Specifications
Note:
Please refer to
Table 2-12
for TAP Signal Group DC specifications and
Table 2-24
for TAP Signal Group
AC specifications.
Figure 2-19. TAP Valid Delay Timing Waveform
Tx = T58: TDO Clock to Output Delay
Ts = T56: TDI, TMS Setup Time
Th = T57: TDI, TMS Hold Time
V = 0.5 * V
TT
TCK
Signal
Tx
Ts
Th
V
Valid
V
Figure 2-20. Test Reset (TRST#), Async GTL+ Input, and PROCHOT# Timing Waveform
V
T
q
T
q
T59 (TRST# Pulse Width), V = 0.5 * V
TT
T38 (PROCHOT# Pulse Width), V = GTLREF
=
Figure 2-21. THERMTRIP# Power Down Sequence
THERMTRIP#
Vcc
V
TT
T
A
T
A
= T39 (THERMTRIP# to removal of power)