Intel BFCBASE Data Sheet - Page 34

Electrical Specifications

34

Document Number: 318080-002

Notes:

1.

The V

CC_MIN

and V

CC_MAX

loadlines represent static and transient limits. Please see

Section 2.11.3

for VCC

overshoot specifications.

2.

Refer to

Table 2-9

for processor VID information.

3.

Refer to

Table 2-10

for V

CC

Static and Transient Tolerance

4.

The load lines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE pins and the

VCC_SENSE2 and VSS_SENSE2 pins. Voltage regulation feedback for voltage regulator circuits must also

be taken from processor VCC_SENSE2 and VSS_SENSE2 pins. Refer to the

Voltage Regulator Module

(VRM) and Enterprise Voltage Regulator Down (EVRD) 11.0 Design Guidelines

for socket load line

guidelines and VR implementation. Please refer to the appropriate platform design guide for details on VR

implementation.

Notes:

1.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2.

V

IL

is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low

value.

3.

V

IH

is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high

value.

4.

V

IH

and V

OH

may experience excursions above V

TT

. However, input signal drivers must comply with the

signal quality specifications.

5.

This is the pull down driver resistance. Refer to processor I/O Buffer Models for I/V characteristics.

Measured at 0.31*V

TT

. R

ON

(min) = 0.225*R

TT

. R

ON

(typ) = 0.250*R

TT

. R

ON

(max) = 0.275*R

TT

6.

GTLREF should be generated from V

TT

with a 1% tolerance resistor divider. The V

TT

referred to in these

specifications is the instantaneous V

TT

.

7.

Specified when on-die R

TT

and R

ON

are turned off. V

IN

between 0 and V

TT

.

8.

This is the measurement at the pin.

Figure 2-8.

Dual-Core Intel® Xeon® Processor 7200 Series V

CC

Static and Transient

Tolerance Load Lines

VID - 0.000

VID - 0.020

VID - 0.040

VID - 0.060

VID - 0.080

VID - 0.100

VID - 0.120

VID - 0.140

VID - 0.160

0

5

10

15

20

25

30

35

40

45

50

55

60

65

70

75

80

85

90

Icc [A]

Vcc [V]

V

CC

Maximum

V

CC

Typical

V

CC

Minimum

Table 2-11.

AGTL+ Signal Group DC Specifications

Symbol

Parameter

Min

Typ

Max

Units

Notes

1

V

IL

Input Low Voltage

-0.10

0

GTLREF-0.10

V

2,4,6

V

IH

Input High Voltage

GTLREF+0.10

V

TT

V

TT

+0.10

V

3,6

V

OH

Output High Voltage

V

TT

- 0.10

N/A

V

TT

V

4,6

R

ON

Buffer On Resistance

10.00

11.50

13.00

Ω

5

I

LI

Input Leakage Current

N/A

N/A

+/-100

μ

A

7,8

Section	Page
1 Introduction	9
1.1 Terminology	11
1.2 State of Data	13
1.3 References	13
2 Electrical Specifications	15
2.1 Front Side Bus and GTLREF	15
2.2 Decoupling Guidelines	15
2.2.1 VCC Decoupling	16
2.2.2 VTT Decoupling	16
2.2.3 Front Side Bus AGTL+ Decoupling	16
2.3 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	16
2.3.1 Front Side Bus Frequency Select Signals (BSEL[2:0])	17
2.3.2 PLL Power Supply	17
2.4 Voltage Identification (VID)	17
2.5 Reserved, Unused, or Test Signals	20
2.6 Front Side Bus Signal Groups	20
2.7 CMOS Asynchronous and Open Drain Asynchronous Signals	22
2.8 Test Access Port (TAP) Connection	22
2.9 Mixing Processors	23
2.10 Absolute Maximum and Minimum Ratings	23
2.11 Processor DC Specifications	24
2.11.1 Flexible Motherboard Guidelines (FMB)	25
2.11.2 Platform Environmental Control Interface (PECI) DC Specifications	35
2.11.3 VCC Overshoot Specification	37
2.11.4 AGTL+ FSB Specifications	38
2.12 Front Side Bus AC Specifications	40
2.13 Processor AC Timing Waveforms	45
3 Mechanical Specifications	57
3.1 Package Mechanical Drawing	57
3.2 Processor Component Keepout Zones	60
3.3 Package Loading Specifications	66
3.4 Package Handling Guidelines	67
3.5 Package Insertion Specifications	67
3.6 Processor Mass Specifications	67
3.7 Processor Materials	67
3.8 Processor Markings	68
3.9 Processor Pin-Out Coordinates	69
4 Pin Listing	71
4.1 Pin Assignments	71
4.1.1 Pin Listing by Pin Name	71
4.1.2 Pin Listing by Pin Number	79
5 Signal Definitions	87
5.1 Signal Definitions.	87
6 Thermal Specifications	95
6.1 Package Thermal Specifications	95
6.1.1 Thermal Specifications	95
6.1.2 Thermal Metrology	102
6.2 Processor Thermal Features	103
6.2.1 Thermal Monitor Features	103
6.2.2 Thermal Monitor	103
6.2.3 Thermal Monitor 2	104
6.2.4 On-Demand Mode	105
6.2.5 PROCHOT# Signal	106
6.2.6 FORCEPR# Signal	106
6.2.7 THERMTRIP# Signal	106
6.3 Platform Environment Control Interface (PECI)	107
6.3.1 Introduction	107
6.3.2 PECI Specifications	108
7 Features	111
7.1 Power-On Configuration Options	111
7.2 Clock Control and Low Power States	111
7.2.1 Normal State	112
7.2.2 HALT or Extended HALT State	112
7.2.3 Stop-Grant State	114
7.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State	115
7.3 Enhanced Intel SpeedStep® Technology	115
7.4 System Management Bus (SMBus) Interface	116
7.4.1 SMBus Device Addressing	117
7.4.2 PIROM and Scratch EEPROM Supported SMBus Transactions	118
7.4.3 Processor Information ROM (PIROM)	119
7.4.4 Checksums	137
7.4.5 Scratch EEPROM	137
8 Boxed Processor Specifications	139
8.1 Introduction	139
8.2 Thermal Specifications	139
8.2.1 Boxed Processor Cooling Requirements	139
9 Debug Tools Specifications	141
9.1 Debug Port System Requirements	141
9.2 Logic Analyzer Interface (LAI)	141
9.2.1 Mechanical Considerations	141

Intel BFCBASE Data Sheet - Page 34

Dual-Core Intel® Xeon® Processor 7200 Series V, Static and Transient

Page 34 highlights