Intel BFCBASE Data Sheet - Page 130
RES3: Reserved 3, 4.3.4.2, L2SIZE: L2 Cache Size, 4.3.4.3, L3SIZE: L3 Cache Size, 4.3.4.4,
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Features 7.4.3.4.1 RES3: Reserved 3 These locations are reserved. Writes to this register have no effect. 7.4.3.4.2 Offset: 25h-26h Bit 15:0 RESERVED 3 0000h-FFFFh: Reserved Description L2SIZE: L2 Cache Size This location contains the size of the level two cache in kilobytes. Writes to this register have no effect. Example: The Intel® Xeon® Processor 7200 Series and 7300 Series has a 2x4MB (8192 KB) L2 cache total. Thus, offset 27 - 28h would contain 2000h. 7.4.3.4.3 Offset: 27h-28h Bit 15:0 L2 Cache Size 0000h-FFFFh: KB Description L3SIZE: L3 Cache Size This location contains the size of the level three cache in kilobytes. Writes to this register have no effect. Example: The Intel® Xeon® Processor 7200 Series and 7300 Series has no L3 cache. Thus, offset 29 - 2Ah will contain 0000h (0 decimal). 7.4.3.4.4 Offset: 29h-2Ah Bit 15:0 L3 Cache Size 0000h-FFFFh: KB Description MAXCVID: Maximum Cache VID This location contains the maximum Cache VID (Voltage Identification) voltage that may be requested via the CVID pins. This field, rounded to the next thousandth, is in mV and is reflected in hex. Writes to this register have no effect. Example: The Intel® Xeon® Processor 7200 Series and 7300 Series does not utilize a Cache VID. Offset 2B - 2Ch will contain 0000h (0 decimal). Offset: 2Bh-2Ch Bit 15:0 Maximum Cache VID 0000h-FFFFh: mV Description 130 Document Number: 318080-002