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Intel BFCBASE Data Sheet - Page 120

Table 7-6., Processor Information ROM Data s Sheet 2 of 3, Features, Cache Data, Package Data

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Features Table 7-6. Processor Information ROM Data Sections (Sheet 2 of 3) Offset/Section 1A - 1Bh 1Ch 1D - 1Eh 1F - 20h # of Bits 2 2 4 4 4 2 16 2 6 16 16 21 - 22h 16 23h 8 24h 8 Cache Data: 25 - 26h 16 27 - 28h 16 29 - 2Ah 16 2B - 2Ch 16 2D - 2Eh 16 2F - 30h 16 31h 8 Package Data: 32 - 35h 32 36h 8 37h 8 Part Number Data: 38 - 3Eh 56 3F - 4Ch 112 4D - 54h 64 55 - 6Eh 208 6Fh 8 Thermal Ref. Data: 70h 8 71 - 72h 16 73h 8 Feature Data: 74 - 77h 32 Function Notes Reserved Processor Core Type Processor Core Family Processor Core Model Processor Core Stepping Reserved Front Side Bus Speed Multiprocessor Support Reserved Maximum Core Frequency Maximum Core VID Minimum Core Voltage TCASE Maximum Checksum Reserved for future use From CPUID From CPUID From CPUID From CPUID Reserved for future use 16-bit binary number (in MHz) 00b = UP,01b = DP,10b = RSVD,11b = MP Reserved 16-bit binary number (in MHz) Maximum VCC requested by VID outputs in mV Minimum processor DC VCC in mV Maximum case temperature spec in °C 1 byte checksum Reserved L2 Cache Size L3 Cache Size Maximum Cache CVID Minimum Cache Voltage Reserved Checksum Reserved for future use 16-bit binary number (in KB) 16-bit binary number (in KB) Maximum VCACHE requested by CVID outputs in mV Minimum processor DC VCACHE in mV Reserved 1 byte checksum Package Revision Reserved Checksum Four 8-bit ASCII characters Reserved for future use 1 byte checksum Processor Part Number Reserved Processor Electronic Signature Reserved Checksum Seven 8-bit ASCII characters Reserved 64-bit identification number Reserved 1 byte checksum Reserved Reserved Checksum Reserved Reserved 1 byte checksum Processor Core Feature Flags From CPUID function 1, EDX contents 120 Document Number: 318080-002

Section	Page
1 Introduction	9
1.1 Terminology	11
1.2 State of Data	13
1.3 References	13
2 Electrical Specifications	15
2.1 Front Side Bus and GTLREF	15
2.2 Decoupling Guidelines	15
2.2.1 VCC Decoupling	16
2.2.2 VTT Decoupling	16
2.2.3 Front Side Bus AGTL+ Decoupling	16
2.3 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	16
2.3.1 Front Side Bus Frequency Select Signals (BSEL[2:0])	17
2.3.2 PLL Power Supply	17
2.4 Voltage Identification (VID)	17
2.5 Reserved, Unused, or Test Signals	20
2.6 Front Side Bus Signal Groups	20
2.7 CMOS Asynchronous and Open Drain Asynchronous Signals	22
2.8 Test Access Port (TAP) Connection	22
2.9 Mixing Processors	23
2.10 Absolute Maximum and Minimum Ratings	23
2.11 Processor DC Specifications	24
2.11.1 Flexible Motherboard Guidelines (FMB)	25
2.11.2 Platform Environmental Control Interface (PECI) DC Specifications	35
2.11.3 VCC Overshoot Specification	37
2.11.4 AGTL+ FSB Specifications	38
2.12 Front Side Bus AC Specifications	40
2.13 Processor AC Timing Waveforms	45
3 Mechanical Specifications	57
3.1 Package Mechanical Drawing	57
3.2 Processor Component Keepout Zones	60
3.3 Package Loading Specifications	66
3.4 Package Handling Guidelines	67
3.5 Package Insertion Specifications	67
3.6 Processor Mass Specifications	67
3.7 Processor Materials	67
3.8 Processor Markings	68
3.9 Processor Pin-Out Coordinates	69
4 Pin Listing	71
4.1 Pin Assignments	71
4.1.1 Pin Listing by Pin Name	71
4.1.2 Pin Listing by Pin Number	79
5 Signal Definitions	87
5.1 Signal Definitions.	87
6 Thermal Specifications	95
6.1 Package Thermal Specifications	95
6.1.1 Thermal Specifications	95
6.1.2 Thermal Metrology	102
6.2 Processor Thermal Features	103
6.2.1 Thermal Monitor Features	103
6.2.2 Thermal Monitor	103
6.2.3 Thermal Monitor 2	104
6.2.4 On-Demand Mode	105
6.2.5 PROCHOT# Signal	106
6.2.6 FORCEPR# Signal	106
6.2.7 THERMTRIP# Signal	106
6.3 Platform Environment Control Interface (PECI)	107
6.3.1 Introduction	107
6.3.2 PECI Specifications	108
7 Features	111
7.1 Power-On Configuration Options	111
7.2 Clock Control and Low Power States	111
7.2.1 Normal State	112
7.2.2 HALT or Extended HALT State	112
7.2.3 Stop-Grant State	114
7.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State	115
7.3 Enhanced Intel SpeedStep® Technology	115
7.4 System Management Bus (SMBus) Interface	116
7.4.1 SMBus Device Addressing	117
7.4.2 PIROM and Scratch EEPROM Supported SMBus Transactions	118
7.4.3 Processor Information ROM (PIROM)	119
7.4.4 Checksums	137
7.4.5 Scratch EEPROM	137
8 Boxed Processor Specifications	139
8.1 Introduction	139
8.2 Thermal Specifications	139
8.2.1 Boxed Processor Cooling Requirements	139
9 Debug Tools Specifications	141
9.1 Debug Port System Requirements	141
9.2 Logic Analyzer Interface (LAI)	141
9.2.1 Mechanical Considerations	141

Match case Limit results 1 per page

Features

120

Document Number: 318080-002

Reserved

Reserved for future use

Processor Core Type

From CPUID

Processor Core Family

From CPUID

Processor Core Model

From CPUID

Processor Core Stepping

From CPUID

Reserved

Reserved for future use

1A - 1Bh

Front Side Bus Speed

16-bit binary number (in MHz)

1Ch

Multiprocessor Support

Reserved

00b = UP,01b = DP,10b = RSVD,11b = MP

Reserved

1D - 1Eh

Maximum Core Frequency

16-bit binary number (in MHz)

1F - 20h

Maximum Core VID

Maximum V

requested by VID outputs in

21 - 22h

Minimum Core Voltage

Minimum processor DC V

in mV

23h

CASE

Maximum

Maximum case temperature spec in °C

24h

Checksum

1 byte checksum

Cache Data:

25 - 26h

Reserved

Reserved for future use

27 - 28h

L2 Cache Size

16-bit binary number (in KB)

29 - 2Ah

L3 Cache Size

16-bit binary number (in KB)

2B - 2Ch

Maximum Cache CVID

Maximum V

CACHE

requested by CVID

outputs in mV

2D - 2Eh

Minimum Cache Voltage

Minimum processor DC V

CACHE

in mV

2F - 30h

Reserved

31h

Checksum

1 byte checksum

Package Data:

32 - 35h

Package Revision

Four 8-bit ASCII characters

36h

Reserved

Reserved for future use

37h

Checksum

1 byte checksum

Part Number Data:

38 - 3Eh

Processor Part Number

Seven 8-bit ASCII characters

3F - 4Ch

112

Reserved

4D - 54h

Processor Electronic

Signature

64-bit identification number

55 - 6Eh

208

Reserved

6Fh

Checksum

1 byte checksum

Thermal Ref. Data:

70h

Reserved

71 - 72h

Reserved

73h

Checksum

1 byte checksum

Feature Data:

74 - 77h

Processor Core Feature

Flags

From CPUID function 1, EDX contents

Table 7-6.

Processor Information ROM Data Sections (Sheet 2 of 3)

Offset/Section

# of

Bits

Function

Notes