Intel BFCBASE Data Sheet - Page 73

Table 4-1. Pin Listing by Pin Name Sheet 5, of 16, Pin Name, Pin No., Signal, Buffer Type, Direction

Page 73 highlights

Pin Listing Table 4-1. Pin Listing by Pin Name (Sheet 5 of 16) Pin Name Pin No. Signal Buffer Type Direction DEFER# C23 DP0# AC18 DP1# AE19 DP2# AC15 DP3# AE17 DRDY# E18 DSTBN0# Y21 DSTBN1# Y18 DSTBN2# Y15 DSTBN3# Y12 DSTBP0# Y20 DSTBP1# Y17 DSTBP2# Y14 DSTBP3# Y11 FERR#/PBE# E27 FORCEPR# A15 GTLREF_ADD_E F9 ND GTLREF_ADD_MI F23 D GTLREF_DATA_E W9 ND GTLREF_DATA_M ID W23 HIT# E22 HITM# A23 IERR# E5 IGNNE# C26 INIT# D6 LINT0 B24 LINT1 G23 LL_IDO B31 LL_ID1 B28 LOCK# A17 MCERR# D7 PECI C28 PROC_ID0 A30 PROC_ID1 B29 PROCHOT# B25 PWRGOOD AB7 REQ0# B19 REQ1# B21 Common Clk Common Clk Common Clk Common Clk Common Clk Common Clk Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Async GTL+ Async GTL+ Power/Other Power/Other Power/Other Power/Other Common Clk Common Clk Async GTL+ Async GTL+ Async GTL+ Async GTL+ Async GTL+ Power/Other Power/Other Common Clk Common Clk Power/Other Power/Other Power/Other Async GTL+ Async GTL+ Source Sync Source Sync Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Output Input Input Input Input Input Input/Output Input/Output Output Input Input Input Input Output Output Input/Output Input/Output Input/Output Output Output Output Input Input/Output Input/Output Table 4-1. Pin Listing by Pin Name (Sheet 6 of 16) Pin Name REQ2# REQ3# REQ4# Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RESET# RS0# RS1# RS2# RSP# SKTOCC# SM_CLK SM_DAT SM_EP_A0 SM_EP_A1 SM_EP_A2 SM_VCC SM_VCC Pin No. Signal Buffer Type Direction C21 C20 B22 A28 A31 B1 B4 B30 C31 D27 D29 E2 Y27 Y28 Y29 AA5 AA28 AB4 AC30 AD4 AD6 AD16 AD28 AD30 AD31 AE8 AE30 Y8 E21 D22 F21 C6 A3 AC28 AC29 AA29 AB29 AB28 AE28 AE29 Source Sync Source Sync Source Sync Common Clk Common Clk Common Clk Common Clk Common Clk Power/Other SMBus SMBus SMBus SMBus SMBus Power/Other Power/Other Input/Output Input/Output Input/Output Input Input Input Input Input Output Input Input/Output Input Input Input Document Number: 318080-002 73

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
  • 79
  • 80
  • 81
  • 82
  • 83
  • 84
  • 85
  • 86
  • 87
  • 88
  • 89
  • 90
  • 91
  • 92
  • 93
  • 94
  • 95
  • 96
  • 97
  • 98
  • 99
  • 100
  • 101
  • 102
  • 103
  • 104
  • 105
  • 106
  • 107
  • 108
  • 109
  • 110
  • 111
  • 112
  • 113
  • 114
  • 115
  • 116
  • 117
  • 118
  • 119
  • 120
  • 121
  • 122
  • 123
  • 124
  • 125
  • 126
  • 127
  • 128
  • 129
  • 130
  • 131
  • 132
  • 133
  • 134
  • 135
  • 136
  • 137
  • 138
  • 139
  • 140
  • 141
  • 142

Document Number: 318080-002
73
Pin Listing
DEFER#
C23
Common Clk
Input
DP0#
AC18
Common Clk
Input/Output
DP1#
AE19
Common Clk
Input/Output
DP2#
AC15
Common Clk
Input/Output
DP3#
AE17
Common Clk
Input/Output
DRDY#
E18
Common Clk
Input/Output
DSTBN0#
Y21
Source Sync
Input/Output
DSTBN1#
Y18
Source Sync
Input/Output
DSTBN2#
Y15
Source Sync
Input/Output
DSTBN3#
Y12
Source Sync
Input/Output
DSTBP0#
Y20
Source Sync
Input/Output
DSTBP1#
Y17
Source Sync
Input/Output
DSTBP2#
Y14
Source Sync
Input/Output
DSTBP3#
Y11
Source Sync
Input/Output
FERR#/PBE#
E27
Async GTL+
Output
FORCEPR#
A15
Async GTL+
Input
GTLREF_ADD_E
ND
F9
Power/Other
Input
GTLREF_ADD_MI
D
F23
Power/Other
Input
GTLREF_DATA_E
ND
W9
Power/Other
Input
GTLREF_DATA_M
ID
W23
Power/Other
Input
HIT#
E22
Common Clk
Input/Output
HITM#
A23
Common Clk
Input/Output
IERR#
E5
Async GTL+
Output
IGNNE#
C26
Async GTL+
Input
INIT#
D6
Async GTL+
Input
LINT0
B24
Async GTL+
Input
LINT1
G23
Async GTL+
Input
LL_IDO
B31
Power/Other
Output
LL_ID1
B28
Power/Other
Output
LOCK#
A17
Common Clk
Input/Output
MCERR#
D7
Common Clk
Input/Output
PECI
C28
Power/Other
Input/Output
PROC_ID0
A30
Power/Other
Output
PROC_ID1
B29
Power/Other
Output
PROCHOT#
B25
Async GTL+
Output
PWRGOOD
AB7
Async GTL+
Input
REQ0#
B19
Source Sync
Input/Output
REQ1#
B21
Source Sync
Input/Output
Table 4-1. Pin Listing by Pin Name (Sheet 5
of 16)
Pin Name
Pin No.
Signal
Buffer Type
Direction
REQ2#
C21
Source Sync
Input/Output
REQ3#
C20
Source Sync
Input/Output
REQ4#
B22
Source Sync
Input/Output
Reserved
A28
Reserved
A31
Reserved
B1
Reserved
B4
Reserved
B30
Reserved
C31
Reserved
D27
Reserved
D29
Reserved
E2
Reserved
Y27
Reserved
Y28
Reserved
Y29
Reserved
AA5
Reserved
AA28
Reserved
AB4
Reserved
AC30
Reserved
AD4
Reserved
AD6
Reserved
AD16
Reserved
AD28
Reserved
AD30
Reserved
AD31
Reserved
AE8
Reserved
AE30
RESET#
Y8
Common Clk
Input
RS0#
E21
Common Clk
Input
RS1#
D22
Common Clk
Input
RS2#
F21
Common Clk
Input
RSP#
C6
Common Clk
Input
SKTOCC#
A3
Power/Other
Output
SM_CLK
AC28
SMBus
Input
SM_DAT
AC29
SMBus
Input/Output
SM_EP_A0
AA29
SMBus
Input
SM_EP_A1
AB29
SMBus
Input
SM_EP_A2
AB28
SMBus
Input
SM_VCC
AE28
Power/Other
SM_VCC
AE29
Power/Other
Table 4-1. Pin Listing by Pin Name (Sheet 6
of 16)
Pin Name
Pin No.
Signal
Buffer Type
Direction