Adaptec 1737100 Programmer Manual - Page 104

AIC-6915 Ethernet LAN Controller Programmer's Manual Table 7-42. InterruptStatus Register (Continued) Reset Bit(s) rw Value Description/Function 19 r/w 0 DmaErrInt: This bit is set on a DMA error. The DMA errors are: Target abort, Master abort, Data parity error (with STOPONPARERR bit set), and bad descriptor. This bit is cleared on a read, or by writing a '1'. 18 r/w 0 TxDataLowInt: This bit is set when transmitting data from a frame that is currently being DMA-transferred, and the number of data bytes stored in the FIFO falls below a programmable threshold as defined by TXFIFOTHRESHOLD. This bit is cleared on a read, or by writing a '1'. Note: When the software receives this interrupt it must tune (raise) the TRANSMITTHRESHOLD. 17 r/w 0 RxCompletionQueue2Int: This bit is set if the number of available entries in Receive Completion Descriptor Queue 2 falls below a programmable threshold. This bit is cleared on a read, or by writing a '1'. 16 r/w 0 RxQ1LowBuffersInt: Indicates a shortage of receive buffers in receive buffer descriptor queue 1. The bit is set when the AIC-6915 tries to fetch a buffer descriptor and the number of buffers available in the queue is less than a programmable threshold as defined in the RXDMACTRL register. The bit is cleared on a read, or by writing a '1'. The number of buffers in the queue is determined by the producer and consumer indexes of the queue. 15 r 0 NormalInterrupt: Is the logical 'OR' of bits 8, 9, 10, 11, 12, 13, & 14. 14 r/w 0 TxFrameCompleteInt: Indicates that at least one complete Ethernet frame has been transmitted (out of the AIC-6915). The AIC-6915 sets the bit after DMA of a Transmit completion descriptor to host memory. This bit is cleared on a read, or by writing a '1'. 13 r/w 0 TxDmaDoneInt: Indicates that at least one complete Ethernet frame has been DMA-transferred from the host buffer to the AIC-6915. The AIC-6915 sets the bit after the DMA-transfer of a transmit completion descriptor to host memory. This bit is cleared on a read, or by writing a '1'. 12 r/w 0 TxQueueDoneInt: Indicates that all frames scheduled for transmit by the software driver were fetched from host buffer and transferred into the internal FIFO. The AIC-6915 sets the bit after the DMA transfer of the transmit completion descriptor of the last frame queued for transmit in either the low priority or high priority transmit DMA queue. This bit is cleared on a read, or by writing a '1'. 11 r/w 0 EarlyRxQ2Int: This bit is set after the DMA transfer of a programmable number of bytes of a received frame. The programmable number is defined by RxEarlyIntThreshold. No status is DMA-transferred at this time. The RxQ2DoneInt interrupt is generated when the whole frame is DMA-transferred. At this time EarlyRxQ2Int is cleared. This bit is cleared on a read, or by writing a '1'. 7-32