Adaptec 1737100 Programmer Manual - Page 145
Type: R/W, Internal Registers Subgroup: MAC Registers, Byte Address, 5004h- 5007h
UPC - 760884136362
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Register Descriptions MacConfig2 Register Type: R/W Internal Registers Subgroup: MAC Registers Byte Address: 5004h- 5007h Table 7-92. MacConfig2 Register Reset Bit(s) rw Value Description/Function 31:16 r/w 0 Reserved: Always read as 0. 15 r 0 TxCRCerr: Transmit Ethernet CRC error status. 14 r 13 r 0 TxIslCRCerr: Transmit ISL (Interswitch Link) CRC error status. 0 RxCRCerr: Receive Ethernet CRC error status. 12 r 0 RxIslCRCerr: Receive ISL CRC error status. 11 r 10 r/w 0 TXCF: Transmit Control Frame. 0 CtlSoftRst: Flow control module soft reset. This bit has no effect on any configuration register state. 9 r/w 0 RxSoftRst: Receive module soft reset. This bit has no effect on any configuration register state. 8 r/w 0 TxSoftRst: Transmit module soft reset. This bit has no effect on any configuration register state. 7 r/w 0 RxISLEn: This bit enables the Rx ISL function. When this bit is cleared, regular Ethernet frames are received. The Address Filtering block qualifies this bit with the first 40-bits of the ISL frame header. 6 r/w 0 BackPressureNoBackOff: When this bit is reset, the Transmit Half Duplex Flow Control bit in the configuration register is ignored. When this bit is set, the transmit engine optionally asserts back pressure with or without the back off delay algorithm dependent on Transmit Half Duplex Flow Control bit. 5 r/w 0 AutoVlanPad: This bit may be set only when PADEN is also set in the MACCONFIG1 register. When AUTOVLANPAD and PADEN are set, the padding is to 60 for a non-VLAN frame and to 64 for VLAN type frames. A VLAN frame is detected when the VLAN type matches the value contained in the VLAN Type register. Note: If the AIC-6915 is required to calculate and add the CRC, then the minimum frame size is 64 for non-VLAN frames, and 68 for a VLAN type frames. 4 r/w 0 MandatoryVLANPad: Mandatory VLAN pad. When this bit is set, padding out to 64-bytes always occurs. 3 r/w 0 TxISLAppen/TxISLCrcEn: Enables ISL hardware CRC generation function. When the bit is reset, the hardware does not append the 4- byte CRC at the end of the frame. Instead, it checks the correctness of the user supplied CRC bytes and flags error accordingly. When this bit is set, hardware a appends 4-byte ISL CRC in addition to normal Ethernet CRC bytes. This bit does not affect the receive operation. 7-73