Adaptec 1737100 Programmer Manual - Page 67

6 w w w w AIC-6915 Internal Registers Summary For the following registers, the 'Byte Address' indicates each registers location in memory space given as a byte offset address from the start of the memory space dedicated for internal registers - 0x50000h. PCI Configuration Header Registers Summary The PCI configuration registers are mapped to Memory Base Address+0x50000 in memory space, 0x00 in configuration spaces and address 0x00 in I/O space. Each register can be accessed on a read using Memory, I/O and configuration commands. Write operations are limited to configuration commands only. Byte Addr 0000h 0004h 0008h 000Ch 0010h 0014h 0018h 001Ch:0024h 0028h 002Ch 0030h 0034h 0038h 003Ch Table 6-1. PCI Configuration Header Registers Summary Data Byte 3 Data Byte 2 Data Byte 1 Data byte 0 Device ID Vendor ID Status Command Base Class Sub Class Program IF Revision ID Built-In Self Test Header Type Latency Timer Cache Line Size LowBaseAdr0 (512-KByte Memory Space, low address bits) HighBaseAdr0 (high address bits) BaseAdr1 (256 byte I/O Space) Reserved Card Bus CIS Pointer SubSystem ID SubSystem Vendor ID Expansion ROM Control Reserved Cap_Ptr Reserved Max Latency Min Gnt Interrupt Pin Interrupt Line 6-1