Adaptec 1737100 Programmer Manual - Page 97

Register Descriptions EEPROM Memory Definition Byte Address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23-124 125 126 127 Table 7-35. EEPROM Memory Definition Description/Function Vendor ID [7:0] Vendor ID [15:8] Device ID [7:0] Device ID [15:8] SubClass [7:0] Base Class [7:0] SubSystem Vendor ID [7:0] SubSystem Vendor ID [15:8] SubSystem Device ID [7:0] SubSystem Device ID [15:8] Interrupt Pin [7:0] Card Bus [7:0] Card Bus [15:8] Card Bus [23:16] Card Bus [31:24] MAC address [7:0] --> MAC Addr Byte 5 (LSB) MAC address [7:0] --> MAC Addr Byte 4 MAC address [7:0] --> MAC Addr Byte 3 MAC address [7:0] --> MAC Addr Byte 2 MAC address [7:0] --> MAC Addr Byte 1 MAC address [7:0] --> MAC Addr Byte 0 (MSB) Minimum Grant [7:0] Maximum Latency [7:0] Reserved Adaptec Standard Format Checksum [7:0] Checksum [15:8] Value 04 90 15 69 00 02 04 90 08 = 62011/TX Rev. 0 09 = 62011/TX Rev. 1 10 = 62022 28 = 62044 20 = 62020/FX 28 = 69011/TX 00 01 00 00 00 00 09 05 FF 00 LSB MSB 7-25