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Adaptec 1737100 Programmer Manual - Page 33

Power Management Mode defined by PCI Bus Power Management Interface

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Transmit Architecture s When the amount of packet data in the FIFO exceeds the "Transmit Threshold," or when the end of packet is already in the FIFO, the "Transmit Frame" state machine signals the MAC to start transmitting the packet. The transmit frame block handles reading packets from the FIFO, MAC interface and FIFO link list management. It also handles "retries" in case collision occurs and handles "aborts" when MAC signals errors. s Built-in decode logic in the transmit frame block dynamically adjusts the priority of BAC arbitration. When the valid data in the FIFO drops below the "High-Priority Transmit FIFO Threshold" during transmission, the priority of transmit DMA is asserted and subsequent Transmit DMA operations are allotted a higher priority in BAC arbitration. Note that this only happens when the Transmit DMA engine and Transmit Frame are working on the same packet. This algorithm is designed to help prevent FIFO underrun. s When the MAC is transmitting a packet, it may encounter network errors such as late collision, excessive deferral, excess collisions, or long packets. The MAC signals the transmit frame, which in turn aborts the current transmission. For normal collisions during the collision window, the MAC signals a "retry" to the Transmit Frame, which in turn retries transmission of these packets. s Error handling routines are implemented in the Transmit Frame to retransmit a packet when transmit FIFO underrun error occurs. The Transmit Frame attempts to retransmit the packet if the start_of_packet data has not been overwritten by a subsequent DMA operation. If the Transmit Frame block cannot re-transmit the packet after three tries, the packet is aborted. The start_of_packet "Producer Index" of the error packet is DMA-transferred back to the host through the "Completion Queue". s As the MAC completes each packet transmission, it advertises the transmit status of this packet. The Statistic Block collects both transmit and receive status and stores them in a local register file. When the mode of "Transmit Complete Interrupt" is on, the transmit status is DMA-transferred to the host. s 64-bit addressing support on all data buffers. The "Descriptor Queue" and the "Completion Queue" are also 64-bit addressing, but they share the same high-order 32-bit addresses (same 4-GByte page). s Power Management Mode defined by PCI Bus Power Management Interface Specification. When the transmit block is put to the "Sleep" mode, all the state machines are reset to "Idle" and then the clock is removed. 3-3

Section	Page
Programmer’s Manual	1
AIC-6915	3
Ethernet LAN Controller	3
Programmer’s Manual	3
Introduction	15
Features	16
General	16
Ethernet	16
DMA	16
Internal Buffer Management	17
32/64-bit PCI	17
Block Diagram	19
Modules	20
Receive Architecture	21
Features	21
Host Data Structures	22
Producer and Consumer Indices	22
Receive DMA Descriptor Queues	22
Normal Mode	23
Polling Mode	23
32-bit Addressing Mode	24
64-bit Addressing Mode	24
Completion/Status Descriptor Queue	24
Accepting frames	25
Completion Descriptor	25
Transmit Architecture	31
Features	31
Transmit Data Structure	34
Transmit Register Set	35
Transmit DMA Buffer Descriptor Queues	35
Type 0, 32-bit Addressing Mode (Frame Descriptor)	35
Type 1 (Generic), 32-bit Addressing Mode (Buffer Descriptor)	38
Type 2 (Generic), 64-bit Addressing Mode (Buffer Descriptor)	38
Type 3, 32-bit Addressing Mode (Frame Descriptor)	39
Type 4, 32-bit Addressing Mode (Frame Descriptor)	39
Transmit Completion Queue Entry	40
PCI Module Architecture	43
Features	43
PCI Block Diagram	45
PCI Master Module	46
64-bit PCI Bus Master	47
Arbitration	48
PCI Target Module	48
Power Management	50
CardBus	51
Retry Function	51
Response to PCI Commands	51
Configuration Address Space	53
I/O Address Space (Direct Access)	53
I/O Address Space (Indirect Access)	53
Expansion ROM Address Space	54
Memory Address Space	54
Parity	54
SERR_	54
PERR_	55
The Command And Byte Enable Bits CBE[3:0]_	55
Illegal Behavior	56
Frame Processor Architecture	57
Features	57
General Architecture & Operation	57
Wake-up Mode	58
Transmit Checksum Accelerator	58
GFP Address Space	59
Internal Registers	59
External Registers	60
Block Diagram	61
Instruction Formats	62
AIC6915 Internal Registers Summary	67
PCI Configuration Header Registers Summary	67
AIC6915 Functional Registers Summary	68
Additional PCI Registers Summary	70
Additional Ethernet Registers Summary	70
Register Descriptions	73
Overview	73
AIC6915 Address Space	74
AIC6915 PCI Address Map	74
Terminology	76
AIC6915 Internal Registers	76
PCI Registers	77
PCI Configuration Header Registers	77
PCI VendorID Register	77
PCI DeviceID Register	77
PCI Command Register	78
PCI Status Register	79
PCI DEVREVID (Device Revision ID) Register	81
PCI Proginfc (Program Interface) Register	81
PCI Subclass Register	81
PCI Baseclass Register	82
PCI Cachesize (Cache Line Size) Register	82
PCI Lattime (Latency Timer) Register	82
PCI Hdrtype (Header Type) Register	83
BIST (Built-in Self Test) Register	83
PCI LowBASEADR0 (Base Address 0) Register	83
PCI HighBASEADR0 (Base Address 0) Register	84
PCI BASEADR1 (Base Address 1) Register	84
PCI CCIS (Configuration Card Information Structure) Register	84
PCI SubSystemVendor ID Register	85
PCI SubSystem ID Register	85
PCI EXPROMCTL (Expansion ROM Control) Register	85
PCI CapPtr (Capabilities List Pointer) Register	86
PCI INTLINSEL (Interrupt Line Select) Register	86
PCI INTPINSEL (Interrupt Pin Select) Register	87
PCI MINGNT (Minimum Grant) Register	87
PCI MAXLAT (Maximum Latency) Register	88
PCI Functional Registers Definition	89
PCIDeviceConfig Register	89
BacControl Register	92
PCIMonitor1 Register	93
PCIMonitor2 Register	94
PMC (Power Management Capabilities) Register	94
PMCSR (Power Management Control/Status) Register	95
PME Event Register	96
Serial EEPROMControlStatus Register	96
EEPROM Memory Definition	97
PCIComplianceTesting Register	98
IndirectIoAddress Register	98
IndirectIoDataPort Register	98
Ethernet Registers	99
General Ethernet Functional Registers	99
GeneralEthernetCtrl Register	99
TimersControl Register	100
CurrentTime Register	102
InterruptStatus Register	103
ShadowInterruptStatus Register	106
InterruptEn Register	107
GPIO Register	108
Transmit Registers	109
TxDescQueueCtrl Register	109
HiPrTxDescQueueBaseAddr Register	111
LoPrTxDescQueueBaseAddr Register	111
TxDescQueueHighAddr Register	112
TxDescQueueProducerIndex Register	112
TxDescQueueConsumerIndex Register	113
TxDmaStatus1	113
TxDmaStatus2	114
TransmitFrameCtrl/Status Register	114
Completion Queue Registers	115
CompletionQueueHighAddr Register	115
TxCompletionQueueCtrl	115
RxCompletionQueue1Ctrl	116
RxCompletionQueue2Ctrl	117
CompletionQueueConsumerIndex	118
CompletionQueueProducerIndex	119
RxHiPrCompletionPtrs	119
Receive Registers	120
RxDmaCtrl	120
RxDescQueue1Ctrl	122
RxDescQueue2Ctrl	124
RxDescQueueHighAddress	124
RxDescQueue1LowAddress	124
RxDescQueue2LowAddress	125
RxDescQueue1Ptrs	125
RxDescQueue2Ptrs	126
RxDmaStatus Register	126
RxAddressFilteringCtrl Register	127
RxFrameTestOut Register	130
PCI Diagnostic Registers	131
PCITargetStatus Register	131
PCIMasterStatus1 Register	132
PCIMasterStatus2 Register	133
PCIDmaLowHostAddr Register	133
BacDmaDiagnostic0 Register	134
BacDmaDiagnostic1 Register	134
BacDmaDiagnostic2 Register	135
BacDmaDiagnostic3 Register	136
MacAddr1 Register	137
MacAddr2 Register	137
PCI CardBus Registers	138
FunctionEvent Register	138
FunctionEventMask Register	139
FunctionPresentState Register	139
ForceFunction Register	140
Additional Ethernet Registers	141
Ethernet Physical Device Registers	141
MIIRegistersAccessPort	141
TestMode Register (TBD)	142
RxFrameProcessorCtrl Register	142
TxFrameProcessorCtrl Register	142
MAC Control Registers	143
MacConfig1 Register	143
MacConfig2 Register	145
BkToBkIPG Register	146
NonBkToBkIPG Register	147
ColRetry Register	147
MaxLength Register	148
TxNibbleCnt Register	148
TxByteCnt Register	148
ReTxCnt Register	149
RandomNumGen Register	149
MskRandomNum Register	150
TotalTxCnt Register	150
RxByteCnt Register	151
TxPauseTimer Register	151
VLANType Register	151
MIIStatus Register	152
Address Filtering Registers	154
Perfect Address Memory Register	154
Perfect Addresses	155
Hash Addresses	155
Hash Priorities	155
VLAN Numbers	155
MAC Statistic Registers	156
Transmit Frame Processor - TxGfpMem	159
Receive Frame Processor - RxGfpMem	159
Ethernet FIFO	159
Sample Driver	161
Code Conventions	161
Producer-Consumer Model for the AIC6915	162
Basic Register Initialization and Reset Sequence	163
Receive Process	167
Receive Completion Descriptor Queue	167
Receive Completion Descriptor Types	167
Type 0 Completion Descriptor	167
Type 1 Completion Descriptor	167
Type 2 Completion Descriptor	168
Type 3 Completion Descriptor	168
Receive Buffer Descriptor Queue	168
Receive Buffer Descriptor Types	168
32-bit buffer descriptor	168
64-bit buffer descriptor	168
Two Receive Queues	169
Receive Producer/Consumer Model	169
Receive Polling Model	169
Receive Initialization	169
Receive Interrupt Handling	175
Transmit Process	176
Transmit Completion Descriptor Queue	176
Transmit Completion Descriptor Types	177
DMA Complete Transmit Completion Descriptor	177
Transmit Complete Transmit Completion Descriptor	177
Transmit Buffer Descriptor Queue	177
Transmit Buffer Descriptor Types	178
Type 0 descriptor	178
Type 1 descriptor	178
Type 2 descriptor	179
Type 3 descriptor	179
Type 4 descriptor	179
Two Transmit Queues	180
Transmit Producer-Consumer Model	180
Transmit Initialization	181
Transmit Handling	185
Transmit Completion Interrupt Handling	187
AIC6915 DDK Features	189

Match case Limit results 1 per page

3-3

Transmit Architecture

■

When the amount of packet data in the FIFO exceeds the “Transmit Threshold,” or

when the end of packet is already in the FIFO, the “Transmit Frame” state machine

signals the MAC to start transmitting the packet. The transmit frame block handles

reading packets from the FIFO, MAC interface and FIFO link list management. It

also handles “retries” in case collision occurs and handles “aborts” when MAC

signals errors.

■

Built-in decode logic in the transmit frame block dynamically adjusts the priority of

BAC arbitration. When the valid data in the FIFO drops below the “High-Priority

Transmit FIFO Threshold” during transmission, the priority of transmit DMA is

asserted and subsequent Transmit DMA operations are allotted a higher priority in

BAC arbitration. Note that this only happens when the Transmit DMA engine and

Transmit Frame are working on the same packet. This algorithm is designed to help

prevent FIFO underrun.

■

When the MAC is transmitting a packet, it may encounter network errors such as

late collision, excessive deferral, excess collisions, or long packets. The MAC signals

the transmit frame, which in turn aborts the current transmission. For normal

collisions during the collision window, the MAC signals a “retry” to the Transmit

Frame, which in turn retries transmission of these packets.

■

Error handling routines are implemented in the Transmit Frame to retransmit a

packet when transmit FIFO underrun error occurs. The Transmit Frame attempts to

retransmit the packet if the start_of_packet data has not been overwritten by a

subsequent DMA operation. If the Transmit Frame block cannot re-transmit the

packet after three tries, the packet is aborted. The start_of_packet “Producer Index”

of the error packet is DMA-transferred back to the host through the “Completion

Queue”.

■

As the MAC completes each packet transmission, it advertises the transmit status of

this packet. The Statistic Block collects both transmit and receive status and stores

them in a local register file. When the mode of “Transmit Complete Interrupt” is on,

the transmit status is DMA-transferred to the host.

■

64-bit addressing support on all data buffers. The “Descriptor Queue” and the

“Completion Queue” are also 64-bit addressing, but they share the same high-order

32-bit addresses (same 4-GByte page).

■

Power Management Mode defined by PCI Bus Power Management Interface

Specification. When the transmit block is put to the “Sleep” mode, all the state

machines are reset to “Idle” and then the clock is removed.