Adaptec 1737100 Programmer Manual - Page 17

Introduction s Supports 32- and 64-bit addressing of Host DMA buffers and DMA descriptor queues s Big/Little endian support for data and descriptors s Special output pin to indicate high-priority PCI request Internal Buffer Management s Large, 8 KByte DMA FIFO (default - 4KByte for transmit, 4-KByte for receive) s Programmable hardware-controlled transmit FIFO thresholds to prevent underrun of transmit FIFO and enhance overall system performance s Unlimited (limited only by the FIFO size) Receive/Transmit frame queueing in the FIFO to handle long PCI bus latencies s Hardware support for handling transmit collisions and FIFO underruns without software intervention 32/64-bit PCI s Compliant with PCI Local Bus Specification revision 2.1 s Compliant with Intel PCI Bus Power Management Interface Specification Rev 1.00 and Microsoft Device Class Power Management Reference Specification (OnNow) s PC 97 ready. Implements all hardware features required by Microsoft's PC 98 design specification s Supports 3.3V and 5.0V PCI signaling s Direct pin out connection to PCI 32/64-bit bus interface s PCI bus master with zero wait state 32/64-bit memory data transfers at 133/266 MBytes/sec, capable to support leading and trailing byte offset for DMA read and write (32-bit) for DMA write s Supports 64-bit addressing in master and target modes s PCI bus master/slave timing referenced to PCI signal PCLK (33.3 MHz max) s PCI bus master programmable Latency Timer, Cache Size, And Interrupt Line Select registers s Automatically senses if the adapter is plugged into a 32-bit or a 64-bit PCI slot. s Supports cache line sizes of 16, 32, 64, 128, and 256 bytes s Supports any combination of active byte enables for all PCI slave accesses s Supports medium PCI target device-select response time s Supports, as a bus master, enhanced PCI System memory data read and write commands: - Memory Read - Memory Read Line - Memory Read Multiple - Memory Write 1-3