Adaptec 1737100 Programmer Manual - Page 57

5 w w w w Frame Processor Architecture Features s Calculate the TCP and UDP checksum s Decode frame type (TCP, UDP, ARP, RARP, IPX, Wake-up, VLAN 802.1q, Ipv4, Ipv6, ICMP, Ethernet 2, IEEE 802/803) s Process Ethernet 2, 802, IPv4, IPv6, TCP and UDP headers s Process receive data on-the-fly. The maximum receive buffer requirement is 8-bytes s Same architecture for both transmit and receive s Ease of implementation, simple decoding logic, no pipeline, fixed instruction format, simple commands s Maximum clock frequency is 25 Mhz. Cycle time of 40 nS is enough to read the instruction RAM and execute the command without any critical pass. s 16 bit data interface. Frame data halfword is sampled when DataValid is asserted s Provides indication when User Data field starts after UDP or TCP headers s Provides partial checksum result for fragmented TCP frame General Architecture & Operation When DATAVALID is asserted, a new 16-bit halfword is read by the processor on the rising edge of clock. The processor has an option to throttle down the data rate by deasserting the signal REQNEXTDATA. New data can be presented to the processor only when REQNEXTDATA is sampled asserted. The interface between the processor and the receive block does not take advantage of that option (REQNEXTDATA is asserted all the time) and assumes that there are at list three instructions the processor can execute between two consecutive assertions of DATAVALID. In the interface with the transmit DMA engine, a 64-bit doubleword is read from the transmit FIFO and 16-bits are presented when ReqNextData is sampled asserted. The processor reads and executes instructions from the instruction memory in 1 clock cycle. The processor executes the instruction and jumps to the next address at the same clock edge if s Loop Counter (LC) is: '0' '1' or '2', and DATAVALID is set, or 5-1