Adaptec 1737100 Programmer Manual - Page 124

AIC-6915 Ethernet LAN Controller Programmer's Manual RxDescQueue2Ctrl Type: R/W Internal Registers Subgroup: Ethernet Functional Registers Byte Address: D8h - DBh Table 7-64. RxDescQueue2Ctrl Register Reset Bit(s) rw Value Description/Function 31:16 r/w RxQ2BufferLength[15:0]: Indicates the length of buffer in bytes. This value must be an integral number of 4-byte words. 15 r 0 Reserved: Always written with zero. 14 r/w 0 RxDescQ2Entries - If this bit is cleared, the Receive Descriptor Queue 2 is 256 entries maximum. If set, it is 2048 entries. 13:8 r 0 Reserved: Always written with zero. 7:0 r/w 0 RxQ2MinDescriptorsThreshold[7:0]: If the number of receive buffers available (producer - consumer) is less than RxQ2MinDescriptorsThreshold, then the AIC-6915 generates a RxQ2LowDescriptors interrupt. This function is active only when a fixed queue size is used. RxDescQueueHighAddress Type: R/W Internal Registers Subgroup: Ethernet Functional Registers Byte Address: DCh - DFh Table 7-65. RxDescQueueHighAddress Register Reset Bit(s) rw value Description/Function 31:0 r/w RxDescQueueHighAddress[31:0]: Indicates the upper 32 bits of the Receive Descriptor Queues in 64-bit addressing mode (RxDescQueue64bitAddress=1). RxDescQueue1LowAddress Type: R/W Internal Registers Subgroup: Ethernet Functional Registers Byte Address: E0h - E3h Table 7-66. RxDescQueue1LowAddress Register Reset Bit(s) rw value Description/Function 31:8 r/w RxDescQ1LowAddress[31:8]: This field indicates the 24 high-order bits of the 32-bit address of the first Receive Buffer Descriptor Queue. The lower 8 bits of address must be 0. This register is written by host driver during initialization and read by the AIC-6915 during a receive DMA operation. Note: The address must be aligned to a 256-byte boundary. 7-52