Adaptec 1737100 Programmer Manual - Page 132

Internal Registers Subgroup: PCI Extra Registers

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AIC-6915 Ethernet LAN Controller Programmer's Manual PCIMasterStatus1 Register Type: R Internal Registers Subgroup: PCI Extra Registers Byte Address: 0104h - 0107h This register is used for diagnostic purposes to read the internal status of a DMA operation. Table 7-74. PCIMasterStatus1 Register Reset Bit(s) rw Value Description/Function 31:25 r 24:18 r 17 r 1 PCIRequestState: Provides the current state of the PCI master request state machine. The total number of states is 7 each state is represented by 1 bit. 1 PCIFrameState: Provides the current state of the PCI master frame state machine. The total number of states is 7 each state is represented by 1 bit. 0 GlobalDmaEn: Provides the status of the PCI Master's Global DMA Enable bit. The bit is a logical 'and' of the following: PCIMstDmaEn, RMA, RTA, (MEMSPACEN + IOSPACEN) 16 r 0 PCIDualAddrCycle: When set, this bit indicates that the last DMA operation was to 64-bit address space. 15 r 0 DmaRead: When set, this bit indicates that the DMA operation is DMA read, otherwise it is a DMA write. 14 r 13 r 12:0 r 1 PCIMstDmaDone: When set, this bit indicates that the PCI master has no pending DMA request. The transfer was completed normally, HCNT has expired (count=0), or abnormally, an unrecoverable error was encountered and the PCI master waits for software intervention. The bit is cleared when the PCI Master receives a request for a new DMA transfer. 0 PCIMstDmaReq: Provides the status of an internal signal that triggers the PCI master to start a new DMA transfer when changing to a '1'. When the signal changes to '0' while PCI Master is active, it terminates the DMA operation when the FIFO is full/empty (PCIFIFOSPACE=0) rather then when HOSTCOUNT=0. The Receive DMA uses this mode of operation since it does not know how long the transfer is when it issues a DMA request. x PCIFifoSpace: The FIFO current status. This bit provides the number of data bytes stored in the FIFO during a DMA write operation and the number of empty bytes in DMA read operation. 7-60

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7-60
AIC-6915 Ethernet LAN Controller Programmer’s Manual
PCIMasterStatus1 Register
Type: R
Internal Registers Subgroup: PCI Extra Registers
Byte Address: 0104h - 0107h
This register is used for diagnostic purposes to read the internal status of a DMA
operation.
Table 7-74. PCIMasterStatus1 Register
Bit(s)
rw
Reset
Value
Description/Function
31:25
r
1
PCIRequestState:
Provides the current state of the PCI master
request state machine. The total number of states is 7 each state is
represented by 1 bit.
24:18
r
1
PCIFrameState:
Provides the current state of the PCI master frame
state machine. The total number of states is 7 each state is
represented by 1 bit.
17
r
0
GlobalDmaEn
:
Provides the status of the PCI Master’s Global
DMA Enable bit. The bit is a logical ‘and’ of the following:
PCIMstDmaEn,
RMA,
RTA,
(
MEMSPACEN
+
IOSPACEN
)
16
r
0
PCIDualAddrCycle
:
When set, this bit indicates that the last DMA
operation was to 64-bit address space.
15
r
0
DmaRead
: When set, this bit indicates that the DMA operation is
DMA read, otherwise it is a DMA write.
14
r
1
PCIMstDmaDone:
When set, this bit indicates that the PCI master
has no pending DMA request. The transfer was completed normally,
HCNT
has expired (count=0), or abnormally, an unrecoverable error
was encountered and the PCI master waits for software
intervention. The bit is cleared when the PCI Master receives a
request for a new DMA transfer.
13
r
0
PCIMstDmaReq
: Provides the status of an internal signal that
triggers the PCI master to start a new DMA transfer when changing
to a ‘1’. When the signal changes to ‘0’ while PCI Master is active, it
terminates the DMA operation when the FIFO is full/empty
(
PCIF
IFO
S
PACE
=0
) rather then when
H
OST
C
OUNT
=0
. The Receive
DMA uses this mode of operation since it does not know how long
the transfer is when it issues a DMA request.
12:0
r
x
PCIFifoSpace:
The FIFO current status. This bit provides the
number of data bytes stored in the FIFO during a DMA write
operation and the number of empty bytes in DMA read operation.