Adaptec 1737100 Programmer Manual - Page 152

AIC-6915 Ethernet LAN Controller Programmer's Manual MIIStatus Register Type: R/W Internal Registers Subgroup: MAC Registers Byte Address: 5070h - 5073h Table 7-106. MIIStatus Register Reset Bit(s) rw value Description/Function 31:5 r 0 Reserved: Always read as 0. 4 r 0 MIILink Fail: MII Link Fail indicator. Setting this bit indicates to the current PHY that the AIC-6915 is continuously scanning for link status. The external PHY's Status register's (Register 1) bit 2, has failed. This bit is cleared during normal operation. Note: This bit is only valid when the SCAN bit is set. Otherwise, the bit has no meaning. 3 r 0 NotValid: Indicates the period of time at the beginning of a scan operation when the external PHY link fail indicator (MIILF) is not valid. 2 r/w 0 Scan: MII management scan. When this bit is set, the host continuously reads the same external MII PHY register specified by MIIPHYAD and MIIREGAD in the MIIAdr register. The MIIADR register must be appropriately set before turning on this bit. The intention use of this bit is to continuously monitor the 'Link Status' bit in MII register 1 (bit 2). 1 r 0 MiiDataValid: MII management data valid. When the serial MII management interface completes a read transaction from an external physical device, the read data and the address of the device (as its mapped in the AIC-6915) are latched, and the MIIDATAVALID bit is set, indicating to the software driver that valid data is ready. Any read or write to the MIIREGISTERSACCESSPORT resets the bit, unless it is a read access, and the target address equals the latched address of the read data. In this case MIIDATAVALID resets only after the data is passed to the host, otherwise it resets immediately. 0 r 0 MiiBusy: MII management busy. The host should poll this bit before reading data from MIIACCESSPORT register or issuing next write command. It is high when MII serial interface is transferring data. 7-80