Adaptec 1737100 Programmer Manual - Page 109
Transmit Registers
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Register Descriptions Transmit Registers TxDescQueueCtrl Register Type: R/W Internal Registers Subgroup: Ethernet Functional Registers Byte Address: 90h - 93h Table 7-46. TxDescQueueCtrl Register Reset Bit(s) rw Value Description/Function 31:24 r/w 23:21 r 2 TxHighPriorityFifoThreshold: Specifies a programmable threshold. When the transmit engine is transmitting data from a frame that is currently being DMA-transferred (End-Of-Frame not yet been fetched from host memory, and the number of transmit data bytes stored in the FIFO drops below the threshold), the transmit DMA engine asserts a high priority DMA request instead of the normal priority one. The internal BAC module arbitrates the receive and transmit DMA requests, detects the request priority, and gives the transmit priority over the receive. The programmable threshold is defined in bytes as: 16*TXHIGHPRIORITYFIFOTHRESHOLD. Note: The TXHIGHPRIORITYFIFOTHRESHOLD register must have values less than or equal to the TXTHRESHOLD register defined in TRANSMITFRAMECTRL register. 0 Reserved: Always written as 0. 20:16 r/w 15:14 r 0 SkipLength: At the front of every frame/buffer transmit DMA descriptor there is a field reserved for software driver usage. The skip length field specifies that field size. The skip length is (SkipLength*8) bytes. If the field is 0, the skip length is 0. 0 Reserved: Always reads 0. 13:8 r/w 4 TxDmaBurstSize: Specifies the number of bytes that the transmit DMA engine requests from the PCI master during its host memory access. Before issuing a new request, the transmit DMA engine checks to see if there is enough room in the FIFO to store (TXDMABURSTSIZE*32) bytes of data. Note: The transmit DMA engine can request the PCI master to fetch more data than TXDMABURSTSIZE*32 in order to align the DMA address to next cacheline boundary if the number of bytes that remains in the buffer is less than a cacheline. In addition, the transmit DMA can request the PCI Master to fetch less data than the burst size if the host buffer is smaller than the burst size. 7 r/w 0 TxDescQueue64bitAddr: If set to a '1', the transmit buffer descriptor queue contains a 64-bit address. The AIC-6915 PCI master must then use the 64-bit addressing mode to access the queue. The high address is defined in the TXDESCQUEUEHIGHADDR register. 7-37
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