Adaptec 1737100 Programmer Manual - Page 80

Target Fast-Back-To-Back Capable. Setting this bit

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AIC-6915 Ethernet LAN Controller Programmer's Manual Bit(s) rw 11 r/w Table 7-6. PCI Status Register (Continued) Reset Value Description/Function 0 STA: Signal Target Abort is set by the target of a PCI bus transaction if it is unable to respond due to a fatal error condition. STA is set inactive during and after assertion of PCI_PCIRST_ or by a write to the STATUS register with bit 11 (=1). The AIC-6915 indicates target-abort for the following conditions: Illegal Overlap. Illegal Write. Illegal Byte Enables. Decoding a non-configuration cycle when in power down mode. 10:9 r 8 r/w 7 r 6:5 r 4 r 3:0 r Note: For the exact conditions under which a Target Abort is indicated by the AIC-6915, refer to PCITargetStatus register. Software must clear both the STA bit and the PCITARGETSTATUS register separately. 1h DST[1:0]: Device Select Timing[1:0] value indicates the longest response time of a PCI device for assertion of PCI_DEVSEL_. Valid values are: 0h for "fast" (1 PCLK), 1h for "medium" (2 PCLKs), 2h for "slow" (3 PCLKs) with value 3h "reserved". Response time for the AIC-6915 is "medium", DST[1:0] = 1h. 0 DPR: Data Parity Reported. Setting this bit indicates that the master of a transaction, with it's PERRESPEN bit set, has either detected PCI_PERR_ asserted or asserted PCI_PERR_. DPR is cleared during and after assertion of PCI_PCIRST_ or by a write to the STATUS register with bit 8 (=1). 1 TFBTBC: Target Fast-Back-To-Back Capable. Setting this bit indicates that the target is capable of accepting fast PCI back-to- back transactions even when the transactions are not to the same agent. The AIC-6915 as a target supports Fast Back-To-Back transactions. TFBTBC is a read only bit. 0 Reserved: Always read as 0 1 NewCapabilities: This bit indicates whether the device implements a list of new capabilities. The AIC-6915 implements PCI power management. If this bit is set, the register at address 34h provides an offset into the PCI configuration space pointing to the location of the first item in the capabilities list. A value of reset means that the device does not implement the capability list. NewCapabilities is a read only bit. 0 Reserved: Always read as 0 7-8

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7-8
AIC-6915 Ethernet LAN Controller Programmer’s Manual
11
r/w
0
STA:
Signal Target Abort is set by the target of a PCI bus
transaction if it is unable to respond due to a fatal error condition.
STA
is set inactive during and after assertion of
PCI_PCIRST_
or
by a write to the
STATUS
register with bit 11 (=1). The AIC-6915
indicates target-abort for the following conditions:
Illegal Overlap.
Illegal Write.
Illegal Byte Enables.
Decoding a non-configuration cycle when in power down mode.
Note
: For the exact conditions under which a Target Abort is
indicated by the AIC-6915, refer to
PCITargetStatus
register.
Software must clear both the
STA
bit and the
P
CI
T
ARGET
S
TATUS
register separately.
10:9
r
1h
DST[1:0]:
Device Select Timing[1:0] value indicates the longest
response time of a PCI device for assertion of
PCI_DEVSEL_
. Valid
values are: 0h for “fast” (1 PCLK), 1h for “medium” (2 PCLKs), 2h
for “slow” (3 PCLKs) with value 3h “reserved”. Response time for
the AIC-6915 is “medium”, DST[1:0] = 1h.
8
r/w
0
DPR:
Data Parity Reported. Setting this bit indicates that the
master of a transaction, with it's
PERRESPEN
bit set, has either
detected
PCI_PERR_
asserted or asserted
PCI_PERR_
.
DPR
is
cleared during and after assertion of
PCI_PCIRST_
or by a write to
the
STATUS
register with bit 8 (=1).
7
r
1
TFBTBC:
Target Fast-Back-To-Back Capable. Setting this bit
indicates that the target is capable of accepting fast PCI back-to-
back transactions even when the transactions are not to the same
agent. The AIC-6915 as a target supports Fast Back-To-Back
transactions.
TFBTBC
is a read only bit.
6:5
r
0
Reserved
: Always read as 0
4
r
1
NewCapabilities:
This bit indicates whether the device
implements a list of new capabilities. The AIC-6915 implements
PCI power management. If this bit is set, the register at address 34h
provides an offset into the PCI configuration space pointing to the
location of the first item in the capabilities list. A value of reset
means that the device does not implement the capability list.
NewCapabilities
is a read only bit.
3:0
r
0
Reserved: Always read as 0
Table 7-6. PCI Status Register
(Continued)
Bit(s)
rw
Reset
Value
Description/Function