Adaptec 1737100 Programmer Manual - Page 96
Internal Registers Subgroup: Ethernet Functional Registers
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AIC-6915 Ethernet LAN Controller Programmer's Manual PME Event Register Type: R/W Internal Registers Subgroup: Ethernet Functional Registers Byte Address: 58h- 5Bh Table 7-33. PME Event Register Reset Bit(s) rw Value Description/Function 31:6 r 0 Reserved: Always read 0. 5 r/w 0 ExtPhyReset: This bit controls the PHYRESET pin directly. Setting EXTPHYRESET is the only way to assert the external pin. 4 r 0 LinkFailStatus: Indicates there is a link fail. This bit is connected directly to the LINKFAIL pin in GPIO bit 0. 3 r/w 0 LinkFailEn: Setting this bit indicates that GPIO bit 0 input mode is used for a Link Fail event. Clearing the bit disables Link Fail from generating PME_. 2 r/w 0 LinkFailLowActive: Clearing this bit indicates that GPIO bit 0 is active high at input mode as a Link Fail indicator. Setting the bit indicates the GPIO bit 0 is active low. 1 r 0 LinkFailEvt: Indicates a link fail event. PME_ is asserted. This bit is cleared when the PME_STATUS bit is cleared. 0 r 0 WakeupEvt: Indicates a wake-up event from the receive module. PME_ is asserted. This bit is cleared when PME_STATUS bit is cleared. Serial EEPROMControlStatus Register Type: R/W Internal Registers Subgroup: PCI Functional Registers Byte Address: 60h - 63h Table 7-34. EEPROMControlStatus Register Reset Bit(s) rw Value Description/Function 31:4 r 3 r 0 Reserved: Always read as 0. 0 InitDone: If the board is set up to read the EEPROM after a hardreset, this bit indicates when the initial reading of the EEPROM is finished. If the board is set up not to read EEPROM after a hardreset, this bit is cleared. 2 r 0 Idle: This is the idle STATUS bit indicating the serial EEPROM state machine is busy or idle. 1 r/w 0 WriteEnable: When this bit is set, it triggers the serial EEPROM interface to issue a 'Write Enable' command. When the command is completed the bit is cleared. 0 r/w 0 WriteDisable: When this bit is set, it triggers the serial EEPROM interface to issue a 'Write Disable' command. When the command is completed the bit is cleared. 7-24