Adaptec 1737100 Programmer Manual - Page 64

AIC-6915 Ethernet LAN Controller Programmer's Manual Name Opcode E Opcode F ExcOnClock ReqNextData LoadWR1 LoadWR2 LoadWR3 LoadWR4 LoadLC BarrelShifterCtrl MaskCtrl MaskSel MuxSelInput2 Table 5-2. Instruction Formats (Continued) Bit Number Description 3:0 Return - Return to main program. When branching from the main program, the next instruction pointer value of the main program is saved in a special register. When executing this command, the information stored in the special register is used as the next instruction address. 3:0 BRONINPUT - When this instruction is executed, the signal InputBranch is checked. If the signal is asserted, the branch address is BRANCHADD[7:0], otherwise its DATA[7:0]. This instruction is specifically used to facilitate having a common program for receive and transmit. On the receive side, INPUTBRANCH is tied to '1'. On the receive side, it is tied to '0'. 4 Instruction is executed or rising edge of clock, otherwise when DATAVALID is asserted. 5 Enables the processor to throttle down the incoming data rate. When asserted, the processor is ready to process the next frame data. 6 ALU output is loaded to WR1 7 ALU output is loaded to WR2 8 ALU output is loaded to WR3 9 ALU output is loaded to WR4 10 Loading Loop Counter. The exact data loaded and the counters operation is defined in Data (INST[47:32]). 11 '0' - Not active (No shift) '1' - Active, shift as specified in Data 12 '0' - Masking is disabled '1' - AND mask is defined by MaskSel 13 '0' - Data[3:1] specifies which nibble of the data is being masked. DATA[15:4] specifies the mask. '1' - DATA[14:12] specifies which nibble of the data is being masked. DATA[11:0] specifies the mask. [16:14] Controls the 8 input mux operation at ALU input 2. '0' - Data '1' - DataIn (Frame Data) '2' - WR1[15:0] '3' - WR2 '4' - WR3 '5' - WR4 '6' - LC '7' - ReadData 5-8