Adaptec 1737100 Programmer Manual - Page 141

Register Descriptions Additional Ethernet Registers The following group of registers control access to the MAC, physical device (MII), transmit FP, receive FP, and Ethernet FIFO. The registers are accessible from PCI memory and indirect I/O space. They are all synchronized to the Ethernet transmit clock and are usually not accessed during normal operation. Ethernet Physical Device Registers MIIRegistersAccessPort Type: R/W Internal Registers Subgroup: MII Registers Byte Address: 2000h - 3FFFh Table 7-87. MIIRegistersAccessPort Register Reset Bit(s) rw Value Description/Function 31 r 30 r 1 MiiDataValid: Same bit as in MIISTATUS register. 1 MiiBusy: Same bit as in MIISTATUS register. 29:16 r 15:0 r/w 0 Reserved: Always read as 0. 0 MiiRegDataPort: The Data port is used for accessing MII registers implemented in external physical device[s]. The Data port resides in a 4-KBytes of address space. Up to 32 external physical devices can be mapped to this space. Each physical device has 32 x 16-bit registers that are mapped to 32 x 32-bits of address space in such a way that the two high bytes are reserved. When the software driver reads any address within the range, the reserved bits are all '0' except bit '31' which provides the 'MiiBusy' status. When the software driver accesses the port and the Serial MII Management port is idle, the AIC-6915 sets the MiiBusy bit and starts an access to the appropriate external physical device. When the access is completed, the AIC-6915 resets the Status bit. Note: accesses to the port while it is 'busy' are ignored. 7-69