Adaptec 1737100 Programmer Manual - Page 52
Cbe[3:0], Nop. Devsel, Cbe_., Nop. Devsel
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AIC-6915 Ethernet LAN Controller Programmer's Manual Table 4-2 lists all 16 PCI commands and the corresponding AIC-6915 response. CBE[3:0]_ 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 Table 4-2. Target Response to PCI Commands Command Abbrev. AIC-6915 Response to Command Interrupt Acknowledge Ignored Special Cycle Ignored I/O Read IORD Supports IORD from the IndirectIoDataPort and IndirectIoAddress registers. When reading the Data Port, the AIC-6915 responds (after verifying that the address matches the assertion of CBE_) in the same manner as if it has received MRDC with an address equal to the one stored in IndirectIoAddress. I/O Write IOWR Supports IOWR to the IndirectIoDataPort and IndirectIoAddress registers. When writing to the Data port, the AIC-6915 responds (after verifying that the address matches the assertion of CBE_) in the same manner as if it has received MWRC with an address equal to the one stored in IndirectIoAddress. Reserved Ignored Reserved Ignored Memory Read MRDC Supports MRDC for different combinations of CBE_. Any unsupported CBE[3:0]_ values result in a target abort. When no CBE[3:0]_ signal is asserted the data cycle is treated as a NOP. DEVSEL_ is asserted using medium speed target response timing. TRDY_ is asserted as soon as the Target has valid read data. The period before TRDY_ is asserted will vary depending on whether the address is internal or external. Memory Write MWRC Supports MWRC for different combinations of CBE_. Any unsupported CBE[3:0]_ values result in a target abort. When no CBE[3:0]_ signal is asserted the data cycle is treated as a NOP. DEVSEL_ is asserted using medium speed target response timing. TRDY_ is asserted as soon as the target is able to complete (data is actually written) the cycle and IRDY_ is asserted. The period before TRDY_ is asserted varies depending on whether the address is internal or external. Reserved RSVD Ignored Reserved RSVD Ignored Configuration CRDC Read Supports CRDC accesses for all registers in single function Configuration register space. All 32-bits are always provided without regard for the CBE[3:0]_ value. When no CBE[3:0]_ signals are asserted the data cycle is treated as a NOP. DEVSEL_ is asserted using medium speed target response timing. 4-10