Adaptec 1737100 Programmer Manual - Page 93

Register Descriptions Table 7-28. BacControl Register (Continued) Reset Bit(s) rw Value Description/Function 1 r/w 0 PREFERRXDMAREQ: Controls BAC's arbitration algorithm. If the bit is set and PREFERTXDMAREQ is cleared, the receive DMA request has priority over transmit DMA data request, otherwise if both bits are cleared, they have equal (round-robin) priority. Note, the AIC-6915 implements an internal dynamically changing control signal that can force PREFERRXDMAREQ to '1'. This control sig- nal is active when the receive FIFO is above a programmable threshold and there is a danger of a FIFO overrun. 0 r/w 1 BacDmaEn: This bit controls the way the BAC responds to DMA transfers. If the bit is cleared, or if PCI master is disabled (GLOBALDMAEN=0), BAC does not respond to any DMA requests. The bit is cleared after: 1. BAC receives a DMA request and (HostAddress + TransferSize > 4 GByte). 2. BAC receives DMA write request and Host address is not on word boundary, or Transfer Size is not 4 word aligned. 3. A DMA transfer is completed and the BAC is operating in single DMA mode. PCIMonitor1 Register Type: R Internal Registers Subgroup: PCI Functional Registers Byte Address: 48h - 4Bh Table 7-29. PCI Monitor1 Register Reset Bit(s) rw Value Description/Function 31:24 r/w 23:16 r/w 15:0 r 0 PCIBusMaxLatency: Provides the peak PCI bus latency measured from the time the software driver reset the register. The latency is presented in PCICLKCYCLE*16 (480nSec) units. 0 PCIIntMaxLatency: Provides the peak PCI interrupt latency measured from the time the software driver reset the register. The latency is presented in PCICLKCYCLE*1K (30.72usec) units. 0 PCISlaveBusUtilization: Provides a count of the total number of PCI clock cycles the AIC-6915 asserts PCI_DEVSEL_ as an active PCI slave, measured from the time the software driver resets the register. The count is presented in PCICLKCYCLE. Reset to 0 if ACTIVETRANSFERCOUNT wraps around to 0. 7-21