Adaptec 1737100 Programmer Manual - Page 99
Ethernet Registers
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Register Descriptions Ethernet Registers The following registers are accessible from PCI configuration, memory, and direct I/O space. They are all synchronized to the Ethernet Transmit clock. General Ethernet Functional Registers GeneralEthernetCtrl Register Type: R/W Internal Registers Subgroup: Ethernet Functional Registers Byte Address: 70h - 73h Table 7-39. GeneralEthernetCtrl Register Reset Bit(s) rw value Description/Function 31:10 r 9 r/w 0 Reserved: Always reads 0. 0 Reserved: Always reads 0. 8 r/w 0 SetSoftInt: When set, the SOFTINT status bit in the INTERRUPTSTATUS register is set. This bit is always read as '0'. 7 r/w 0 Reserved: Always reads 0. 6 r/w 0 Reserved: Always reads 0. 5 r/w 0 TxGfpEn: When set, the transmit general frame processor is enabled, otherwise it remains in the reset state. 4 r/w 0 RxGfpEn: When set, the receive general frame processor is enabled, otherwise it remains in the reset state. 3 r/w 0 TxDmaEn: Controls the transmit DMA operation. When the bit is cleared the transmit module (data, buffer descriptors, completion descriptors) does not issue any DMA requests. The bit is cleared by the software driver, or when the PCI master encounters a PCI error which should disable the DMA operation. Note that only when the TXDMAEN bit is cleared can the software driver access and write the transmit DMA buffer queue consumer index and the transmit DMA completion queue producer index. 2 r/w 0 RxDmaEn: Controls the receive DMA operation. When the bit is cleared, the receive DMA module (data, buffer descriptors, completion descriptors) does not issue any DMA requests. The bit is cleared when the PCI master encounters a PCI error which should disable the DMA operation. Note that only when the RXDMAEN bit is cleared can the software driver access and write the receive DMA buffer queue consumer index and the receive DMA completion queue producer index. 1 r/w 0 TransmitEn: Controls the transmit engine operation. When the bit is cleared, no data is transmitted. This bit has no effect on the transmit DMA operation. 0 r/w 0 ReceiveEn: Controls the receive engine operation. When the bit is cleared, all newly received frames are discarded. This bit has no effect on the receive DMA operation. 7-27