Adaptec 1737100 Programmer Manual - Page 120

Receive Registers

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AIC-6915 Ethernet LAN Controller Programmer's Manual Bit(s) 9:0 Table 7-61. RxHiPrCompletionPtrs Register (Continued) Reset rw Value Description/Function r/w 0 RxCompletionQ2ConsumerIndex: Written by software driver and read by the AIC-6915. The software driver increments or writes a new index to free space in the queue. Receive Registers RxDmaCtrl Type: R/W Internal Registers Subgroup: Ethernet Functional Registers Byte Address: D0h - D3h Table 7-62. RxDmaCtrl Register Reset Bit(s) rw Value Description/Function 31 r/w 0 RxReportBadFrames: If set, the AIC-6915 reports the status for rejected frames to the host, although it reuses the buffers for the next frame. Otherwise, the AIC-6915 does not report any status when it receives a bad frame, but only updates internal statistics. This bit can be set only if long-completion descriptor mode is selected. 30 r/w 0 RxDmaShortFrames: If set, the receive DMA module accepts frames shorter than 64 bytes. Otherwise, they are rejected. Note: Although this register is implemented in the receive DMA module, it actually affects the operation of receive frames. 29 r/w 0 RxDmaBadFrames: If set, accept frames with dribble nibble, code violation, or cut off due to FIFO overflow. Otherwise, they are rejected. 28 r/w 0 RxDmaCrcErrorFrames: If set, frames with CRC errors are accepted. If the bit is cleared they are rejected. 27 r/w 0 RxDmaControlFrame: If this bit is set the AIC-6915 transfers MAC control frames other than pause frames to the host. 26 r/w 0 RxDmaPauseFrame: If this bit is set the AIC-6915 transfers MAC control pause frames to the host. 25:24 r/w 0 RxChecksumMode: This field determines whether to use the checksum to accept frames. The encoding is as follows: '00' - Ignore the checksum. '01' - Reject TCP frames with a bad checksum. '10' - Reject both TCP and UDP frames with bad checksums. '11' - reserved. 23 r/w 0 RxCompletionQ2Enable: If this bit is set, the second completion queue is enabled. The results of high-priority frames are DMAtransferred to the high-priority completion queue. When the second queue is enabled, the FP can override which queue to use. 7-48

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7-48
AIC-6915 Ethernet LAN Controller Programmer’s Manual
Receive Registers
RxDmaCtrl
Type: R/W
Internal Registers Subgroup: Ethernet Functional Registers
Byte Address:
D0h - D3h
9:0
r/w
0
RxCompletionQ2ConsumerIndex:
Written by software driver and
read by the AIC-6915. The software driver increments or writes a
new index to free space in the queue.
Table 7-62. RxDmaCtrl Register
Bit(s)
rw
Reset
Value
Description/Function
31
r/w
0
RxReportBadFrames:
If set, the AIC-6915 reports the status for
rejected frames to the host, although it reuses the buffers for the next
frame. Otherwise, the AIC-6915 does not report any status when it
receives a bad frame, but only updates internal statistics. This bit
can be set only if long-completion descriptor mode is selected.
30
r/w
0
RxDmaShortFrames:
If set, the receive DMA module accepts frames
shorter than 64 bytes. Otherwise, they are rejected.
Note
: Although this register is implemented in the receive DMA
module, it actually affects the operation of receive frames.
29
r/w
0
RxDmaBadFrames:
If set, accept frames with dribble nibble, code
violation, or cut off due to FIFO overflow. Otherwise, they are
rejected.
28
r/w
0
RxDmaCrcErrorFrames:
If set, frames with CRC errors are accepted.
If the bit is cleared they are rejected.
27
r/w
0
RxDmaControlFrame:
If this bit is set the AIC-6915 transfers MAC
control frames other than pause frames to the host.
26
r/w
0
RxDmaPauseFrame:
If this bit is set the AIC-6915 transfers MAC
control pause frames to the host.
25:24
r/w
0
RxChecksumMode:
This field determines whether to use the
checksum to accept frames. The encoding is as follows:
‘
00
’ - Ignore the checksum.
‘
01
’ - Reject TCP frames with a bad checksum.
‘
10
’ - Reject both TCP and UDP frames with bad checksums.
‘
11
’ - reserved.
23
r/w
0
RxCompletionQ2Enable:
If this bit is set, the second completion
queue is enabled. The results of high-priority frames are DMA-
transferred to the high-priority completion queue. When the second
queue is enabled, the FP can override which queue to use.
Table 7-61. RxHiPrCompletionPtrs Register
(Continued)
Bit(s)
rw
Reset
Value
Description/Function