Adaptec 1737100 Programmer Manual - Page 91

Table 7-27., PCIDeviceConfig Register Continued

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Register Descriptions Table 7-27. PCIDeviceConfig Register (Continued) Reset Bit(s) rw Value Description/Function 6 r/w 0 StopOnPerr: Specifies the behavior of the PCI master when a data parity error is encountered during an active DMA operation. If the bit is asserted, the PCI master stops the transfer as soon as it detects/receives a data parity error. The PCIMstDmaEn, TxDmaEn and RxDmaEn bits are reset, and driver software intervention is required to resume operation. 5 r/w 0 AbortOnAddrParityErr: This bit controls the behavior of the PCI target state machine in response to a bad parity during an address phase. If reset, (default) the target state machine claims the transaction despite the bad parity. If set to '1', the target state machine does not claim the cycle, and thereby cause a master-abort condition for the other agent. 4 r/w 0 EnIncrement: when the bit is asserted and completing a successful read/write to I/O Data Port register with PCI_CBE_[3] asserted, the address stored in DATAADD register is incremented by 1, otherwise the address is not changed. Note: The address is incremented only if the PCI cycle is completed successfully. 3 r/w 0 Reserved: Always read as 0. 2 r 0 System64: This bit indicates the system bus size. Setting the bit indicates a 64-bit system. Clearing the bit indicates a 32-bit system. 1 r/w 0 Force64: Setting this bit forces master mode to be 64-bit transfers if SYSTEM64 = 0. Clearing the bit indicates that the size of master mode transfers depends on the SYSTEM64 bit. 0 r/w 0 SoftReset: When set, this bit produces a reset pulse which performs in the same way as if PCI_PCIRST_ (except for the Configuration Header register space which remains unchanged). The reset pulse is transferred to the other clock domain and remains asserted until the entire AIC-6915 is initialized. As long as the initialization process takes place (no more than 1 other clock period + 4 PCLK periods) the PCI Target does not respond to any PCI cycles. SoftReset is a self clearing bit that always read as '0'. Note, when soft reset is performed the serial EPROM is not read again. The PHYRESET pin is not affected by the SOFTRESET bit. 7-19

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7-19
Register Descriptions
6
r/w
0
StopOnPerr:
Specifies the behavior of the PCI master when a data
parity error is encountered during an active DMA operation. If the
bit is asserted, the PCI master stops the transfer as soon as it
detects/receives a data parity error. The
PCIMstDmaEn
,
TxDmaEn
and
RxDmaEn
bits are reset, and driver software intervention is
required to resume operation.
5
r/w
0
AbortOnAddrParityErr:
This bit controls the behavior of the PCI
target state machine in response to a bad parity during an address
phase. If reset, (default) the target state machine claims the
transaction despite the bad parity. If set to ‘1’, the target state
machine does not claim the cycle, and thereby cause a master-abort
condition for the other agent.
4
r/w
0
EnIncrement:
when the bit is asserted and completing a successful
read/write to I/O Data Port register with
PCI_CBE_[3]
asserted, the
address stored in
DATAADD
register is incremented by 1,
otherwise the address is not changed.
Note
: The address is incremented only if the PCI cycle is completed
successfully.
3
r/w
0
Reserved:
Always read as 0.
2
r
0
System64:
This bit indicates the system bus size. Setting the bit
indicates a 64-bit system. Clearing the bit indicates a 32-bit system.
1
r/w
0
Force64:
Setting this bit forces master mode to be 64-bit transfers if
S
YSTEM
64
= 0. Clearing the bit indicates that the size of master mode
transfers depends on the
S
YSTEM
64
bit.
0
r/w
0
SoftReset:
When set, this bit produces a reset pulse which performs
in the same way as if
PCI_PCIRST_
(except for the Configuration
Header register space which remains unchanged). The reset pulse is
transferred to the other clock domain and remains asserted until the
entire AIC-6915 is initialized. As long as the initialization process
takes place (no more than 1 other clock period + 4 PCLK periods)
the PCI Target does not respond to any PCI cycles. SoftReset is a self
clearing bit that always read as ‘0’. Note, when soft reset is
performed the serial EPROM is not read again. The
P
HY
R
ESET
pin is
not affected by the
S
OFT
R
ESET
bit.
Table 7-27.
PCIDeviceConfig Register (Continued)
Bit(s)
rw
Reset
Value
Description/Function