Adaptec 1737100 Programmer Manual - Page 88

AIC-6915 Ethernet LAN Controller Programmer's Manual PCI MAXLAT (Maximum Latency) Register Type: R Internal Registers Subgroup: PCI Configuration Header Byte Address: 3Fh Table 7-26. Maximum Latency Register Reset Bit(s) rw Value Description/Function 7:0 r 06h MAXLAT[7:0]: Always read as 06h. The Maximum Latency register indicates how often the device needs to gain access to the PCI bus. The value read from the register specifies a period of time in units of 0.25 microseconds. Assuming an average required transfer rate of 30MByte/Sec (25M + 5M overhead), and an average burst size of 64 bytes (which takes 0.48usec based on clock of 33MHz and 4 bytes per Data phase) the maximum latency would be: 30MByte/Sec = 64 / (0.48usec+MaxLat) MaxLat = (64 / 30) - 0.48 = 1.65333usec =~ 1.50 usec The AIC-6915's MAXLAT register value is 6h, which is 1.5usec/0.25usec. Note: For smaller burst sizes or higher required data transfer rates this number has to change. The default value can be changed to a value read from an external serial EEPROM if the BR_A1 signal pin is asserted when PCIRST_ is deasserted. 7-16