Adaptec 1737100 Programmer Manual - Page 58
Wake-up Mode, Transmit Checksum Accelerator
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AIC-6915 Ethernet LAN Controller Programmer's Manual s LC= 0, 1 or 2, and EXCONCLOCK is set, or s Read/Write instruction is executed and the Input IOREADY is sampled asserted. Note: EXCONCLOCK is a bit in the instruction. The loop counter is decremented by 2 every clock cycle if EXCONCLOCK=1, or if DATAVALID is asserted. The loop counter stops when reaching its terminal count of zero. Decrementing the counter by 2 each time assures that incoming data is on a byte boundary. The processor writes 16-bit data (ALU output) to a 16-bit address space defined in the instruction. It can also read a location pointed by an address defined in the instruction, and load the data to any of its working registers. The data read is passing through the ALU and can also be processed if specified by the instruction. Wake-up Mode When the chip is functioning in power down mode, the GFP is loaded with a program designed for decoding wake-up frames. When the GFP decodes a wake-up frame it asserts the status bits WAKEUPFRAME and GFPDONE. External logic is responsible to execute all the processes required by Microsoft On-Now specification, including assertion of the PME_ signal. When working in wake-up mode, the GFP should not be reset between frames. Instead the input STARTOFFRAME is asserted to signal the beginning of a new incoming Ethernet frame. This feature enables the GFP to try and decode multiple frame types in a serial manner. Transmit Checksum Accelerator To accelerate the checksum calculation the 25 MHz clock must be connected to the GFP at all times. When the GFP is ready to process the frame in a loop, it asserts the STARTUSERDATA status bit. At this point the transmit DMA engine presents (instead of the regular frame data) a sum of two or more (up to four) 16-bit halfwords that are computed in parallel (at one clock cycle), with an indication (GFPBYTECNT[3:0]) of how many bytes of frame data are included in the sum. The GFP then decrements the LC by the number given by the transmit DMA engine. The maximum number is 8 = 2*4 and the minimum number is three. The GFP implements a 16-bit frame counter, GfpFrameCnt[15:0], which counts the number of GFPDATAVALID from the beginning of the Ethernet frame. The Transmit DMA engine monitors the counters 3 least significant bits and activates the accelerator only when they are '0'. This guarantees that the accelerator is activated only when 8 bytes of data is read from the transmit FIFO. The transmit DMA engine must monitor LC[15:0] to detect when the number of bytes still requiring processing is below 3, at which time the accelerator hardware is disconnected from the data path. When the transmit DMA engine presents a sum of 2 or more halfwords instead of the regular frame data, it must also provide 2 bits of carry information (GFPDATAIN[17:16]). The transmit DMA engine can monitor the status register bits all the time since these are available as outputs also. If it can be guaranteed that the TCP/UDP Checksum field is presented as 0 x 0 to the GFP, then a few instructions can be saved. 5-2