Adaptec 1737100 Programmer Manual - Page 60
External Registers
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AIC-6915 Ethernet LAN Controller Programmer's Manual Table 5-1. Status/Control Register (Continued) Bit Description 16 StopTxDma - If set, indicates the transmit DMA engine must freeze its operation and wait for software intervention 17 VlanFrame - If set, indicates a VLAN 802.1q frame 18 DiscardFrame - If set, indicates the frame being processed must be discarded (transmit or receive) 19 PartialChecksumValid - If set, indicates that Wreg1 stores a valid partial checksum for a fragmented frame. 20 BypassMaskingIntTimer - If set, indicates the receive DMA is requested to interrupt the host immediately after a completion descriptor for current frame is DMA-transferred to host memory. 21 DmaHeaderOnly - If set, indicates the receive DMA is requested to the DMA only the header of the frame being processed. The header size equals 2*(1+GfpFrameCnt[15:0]) bytes at the moment DmaHeaderOnly changes to '1'. 22 StartUserData - When set, this bit indicates that GFPFRAMECNT[15:0] stores the offset to the beginning of user data from the start of the Ethernet frame, in 16-bit halfword units. 23 IcmpFrame - If set, indicates an ICMP frame. 24 SelDescQueue0 - If set, indicates the receive DMA engine is requested to DMA the frame to buffers specified in Descriptor Queue 0. 25 SelDescQueue1 - If set, indicates the receive DMA engine is requested to DMA the frame to buffers specified in Descriptor Queue 1. 26 SelCompQueue0 - If set, indicates the receive DMA engine is requested to DMA the completion descriptor for this frame to queue 0. 27 SelCompQueue1 - If set, indicates the receive DMA engine is requested to DMA the completion descriptor for this frame to queue 0. 28 Reserved 29 Reserved 30 Reserved 31 Reserved External Registers The external registers are used as a standard way to communicate with other modules. All defined external registers are write-only (from the GFPs point of view). They are used for providing information to external devices. The following external addresses are defined: '0x00' - GFPSTATUS[15:0]. '0x01' - GFPSTATUS[31:16]. '0x02' - TCP/UDP checksum location '0x03' - TCP/UDP checksum value '0x04' - IP checksum location register '0x05' - IP checksum value register '0x06' - TCP/UDP frame size '0x0D - 0x07' - Reserved '0x0E' - GFP Receive Interrupt. '0x0F' - GFP Transmit Interrupt 5-4