Adaptec 1737100 Programmer Manual - Page 43
PCI Module Architecture
![]() |
UPC - 760884136362
View all Adaptec 1737100 manuals
Add to My Manuals
Save this manual to your list of manuals |
Page 43 highlights
4 w w w w PCI Module Architecture Features s Compliant with PCI Local Bus Specification, Revision 2.1 s Compliant with Intel PCI Bus Power Management Interface Specification Rev 1.00 and Microsoft Device Class Power Management Reference Specification (OnNow) s PC 97 ready. Implements all hardware features required by Microsoft's PC 97 design specification s Supports 3.3V and 5.0V PCI signaling s Direct pin out connection to PCI 32/64-bit bus interface s PCI bus master with zero wait state 32/64-bit memory data transfers at 133/266 MBytes/sec, capable of supporting leading and trailing byte offset for DMA read and write (32-bit) for DMA write. s Supports PCI Single/Dual address cycles in target mode and Single/Dual address cycles in master mode. s PCI bus master/slave timing referenced to PCI signal PCLK (33.3 MHz max) s PCI bus master programmable Latency Timer, Cache Size, and Interrupt Line Select registers s Supports cache line sizes of 4, 8, 16, 32, and 64 words s Supports any combination of active byte enables for all PCI slave accesses s Supports medium PCI target device-select response time s Supports, as a bus master, enhanced PCI System memory data read and write commands: - Memory Read - Memory Read Line - Memory Read Multiple - Memory Write - Memory Write And Invalidate s Supports PCI bus address and data parity generation and checking. 4-1
![](/manual_guide/products/adaptec-1737100-programmer-manual-d6d6d7d/43.png)