Adaptec 1737100 Programmer Manual - Page 122

Type: R/W, Internal Registers Subgroup: Ethernet Functional Registers, Byte Address: D4h - D7h, Many

Get Adaptec 1737100 - 62044 SGL ENET PCI 4CH PDF manuals and user guides
UPC - 760884136362
View all Adaptec 1737100 manuals
Add to My Manuals
Save this manual to your list of manuals

Page 122 highlights

AIC-6915 Ethernet LAN Controller Programmer's Manual Table 7-62. RxDmaCtrl Register (Continued) Reset Bit(s) rw Value Description/Function 11:8 r/w 6h RxHighPriorityThreshold[3:0]: If more than RxHighPriorityThreshold * 256 ± 128 bytes are in the FIFO, increase the priority of receive DMA requests. The high-priority indication is used by the internal arbiter (BAC) to determine which module (transmit or receive) to service next. The programmable threshold in bytes is 16 * RXHIGHPRIORITYFIFOTHRESHOLD. 7 r 0 RxFpTestMode: If this bit is set the FP is not set between frames. Used for diagnostic purposes only. 6:0 r/w 4h RxBurstSize[6:0]: Specifies the amount of data to write at one time, times 32 bytes. The receive DMA engine starts a transfer only if RxBurstSize of data or the end-of-frame is stored in the FIFO. If a burst is greater than or equal to a cacheline, and it does not end on a cache line boundary, the burst size for that burst is rounded down to end of the previous cacheline. This causes the next burst to be cache-line aligned. RxDescQueue1Ctrl Type: R/W Internal Registers Subgroup: Ethernet Functional Registers Byte Address: D4h - D7h Note: Many of the bits in RXDESCQUEUE1CTRL affect descriptor queue 2 as well. Table 7-63. RxDescQueue1Ctrl Register Reset Bit(s) rw Value Description/Function 31:16 r/w 15 r/w x RxQ1BufferLength[15:0]: Indicates the length of buffer (in bytes) in descriptor queue 1. This value must be an integral number of 4-byte words. 0 RxPrefetchDescriptorsMode: Setting this bit places the AIC-6915 in Prefetch mode. The AIC-6915 does not wait for the producer to be updated before fetching a buffer descriptor. When it needs a descriptor, it always reads the next one. If the Valid bit in the descriptor is set, the AIC-6915 uses the descriptor. If not, it generates an RXQ1LOWBUFFERS or RXQ2LOWBUFFERS interrupt, then waits for the host to place more descriptors in the queue and to write any value to the producer. This control bit is used for both descriptor queues. 14 r/w 0 RxDescQ1Entries - If 0, the receive descriptor queue 1 is 256 entries maximum. If set, it is 2048 entries maximum. 7-50

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
  • 79
  • 80
  • 81
  • 82
  • 83
  • 84
  • 85
  • 86
  • 87
  • 88
  • 89
  • 90
  • 91
  • 92
  • 93
  • 94
  • 95
  • 96
  • 97
  • 98
  • 99
  • 100
  • 101
  • 102
  • 103
  • 104
  • 105
  • 106
  • 107
  • 108
  • 109
  • 110
  • 111
  • 112
  • 113
  • 114
  • 115
  • 116
  • 117
  • 118
  • 119
  • 120
  • 121
  • 122
  • 123
  • 124
  • 125
  • 126
  • 127
  • 128
  • 129
  • 130
  • 131
  • 132
  • 133
  • 134
  • 135
  • 136
  • 137
  • 138
  • 139
  • 140
  • 141
  • 142
  • 143
  • 144
  • 145
  • 146
  • 147
  • 148
  • 149
  • 150
  • 151
  • 152
  • 153
  • 154
  • 155
  • 156
  • 157
  • 158
  • 159
  • 160
  • 161
  • 162
  • 163
  • 164
  • 165
  • 166
  • 167
  • 168
  • 169
  • 170
  • 171
  • 172
  • 173
  • 174
  • 175
  • 176
  • 177
  • 178
  • 179
  • 180
  • 181
  • 182
  • 183
  • 184
  • 185
  • 186
  • 187
  • 188
  • 189
  • 190
7-50
AIC-6915 Ethernet LAN Controller Programmer’s Manual
RxDescQueue1Ctrl
Type: R/W
Internal Registers Subgroup: Ethernet Functional Registers
Byte Address: D4h - D7h
Note
: Many of the bits in
R
X
D
ESC
Q
UEUE
1C
TRL
affect descriptor queue 2 as well.
11:8
r/w
6h
RxHighPriorityThreshold[3:0]:
If more than
RxHighPriorityThreshold * 256 ± 128
bytes are in the FIFO,
increase the priority of receive DMA requests. The high-priority
indication is used by the internal arbiter (BAC) to determine which
module (transmit or receive) to service next. The programmable
threshold in bytes is
16 * R
X
H
IGH
P
RIORITY
F
IFO
T
HRESHOLD
.
7
r
0
RxFpTestMode:
If this bit is set the FP is not set between frames.
Used for diagnostic purposes only.
6:0
r/w
4h
RxBurstSize[6:0]:
Specifies the amount of data to write at one time,
times 32 bytes. The receive DMA engine starts a transfer only if
RxBurstSize
of data or the end-of-frame is stored in the FIFO.
If a burst is greater than or equal to a cacheline, and it does not end
on a cache line boundary, the burst size for that burst is rounded
down to end of the previous cacheline. This causes the next burst to
be cache-line aligned.
Table 7-63. RxDescQueue1Ctrl Register
Bit(s)
rw
Reset
Value
Description/Function
31:16
r/w
x
RxQ1BufferLength[15:0]:
Indicates the length of buffer (in bytes) in
descriptor queue 1. This value must be an integral number of 4-byte
words.
15
r/w
0
RxPrefetchDescriptorsMode:
Setting this bit places the AIC-6915 in
Prefetch mode. The AIC-6915 does not wait for the producer to be
updated before fetching a buffer descriptor. When it needs a
descriptor, it always reads the next one. If the Valid bit in the
descriptor is set, the AIC-6915 uses the descriptor. If not, it generates
an
R
X
Q1L
OW
B
UFFERS
or
R
X
Q2L
OW
B
UFFERS
interrupt, then waits
for the host to place more descriptors in the queue and to write any
value to the producer.
This control bit is used for both descriptor queues.
14
r/w
0
RxDescQ1Entries
- If 0, the receive descriptor queue 1 is 256 entries
maximum. If set, it is 2048 entries maximum.
Table 7-62. RxDmaCtrl Register
(Continued)
Bit(s)
rw
Reset
Value
Description/Function