Adaptec 1737100 Programmer Manual - Page 79
STATUS, PCI_PCIRST, DPE, SSE, RMA, RTA, STA, PCIDeviceConfig, PCIInt, GeneralInterruptStatus
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Register Descriptions Table 7-5. PCI Command Register (Continued) Bit(s) rw Reset Value Description/Function 0 r/w 0 ISPACEEN: I/O Space Enable. Setting this bit enables the AIC-6915 to respond to PCI I/O transactions. When ISPACEEN is inactive the AIC-6915 does not respond to I/O cycles. PCI Status Register Type: R/W Internal Registers Subgroup: PCI Configuration Header Byte Address: 06h - 07h The STATUS register is used to record status information for PCI bus related events. Read transactions of the STATUS register access the currently stored status information. Write transactions to the STATUS register are not used to store data but rather to clear those bits that are set. The STATUS register is forced to be inactive when PCI_PCIRST_ is asserted. The STATUS register may be read at any time in Configuration, I/O, or memory Space. If at least one of the status bits: DPE, SSE, RMA, RTA, STA or DPR is asserted and the corresponding enable bit, implemented in PCIDeviceConfig register, is also asserted, then PCIInt is asserted. PCIInt is an internal interrupt status bit implemented in GeneralInterruptStatus register. Bit(s) rw 15 r/w 14 r/w 13 r/w 12 r/w Reset Value 0 0 0 0 Table 7-6. PCI Status Register Description/Function DPE: The Detected Parity Error bit is set when a 36-bit even-parity error is detected by the AIC-6915 (as a target) during an Address phase or a Write Data phase, and by the transaction master during a Read Data phase. DPE is set inactive during and after assertion of PCI_PCIRST_ or by a write to the STATUS register with bit 15 (=1). SSE: Signal System Error. The AIC-6915 sets the SSE bit only when PERRESPEN and SERRESPEN are set for detected address parity errors. RMA: Received Master Abort is set when the AIC-6915-generated transaction is terminated by the AIC-6915 due to no response from the intended target by the sixth (for SAC) or seventh (for DAC ) PCLK after the AIC-6915 asserted FRAME_. The AIC-6915 releases the bus on the next PCLK and does not retry the transaction. Software/firmware intervention is required for the AIC-6915 to continue master transactions. RMA is set inactive during and after assertion of PCI_PCIRST_ or by a write to the STATUS register with bit 13 (=1). RTA: Received Target Abort is set when the AIC-6915, as a PCI bus master, generates a transaction terminated with Target-Abort indication. RTA is set inactive during and after assertion of PCI_PCIRST_ or by a write to the STATUS register with bit 28 (=1). When an Target-Abort indication is received, the AIC-6915 does not retry the transaction and software/firmware intervention is required for the AIC-6915 to continue master transactions. 7-7