Adaptec 1737100 Programmer Manual - Page 50

AIC-6915 Ethernet LAN Controller Programmer's Manual Power Management The PCI bus power management defined four power states. D0 indicates the "On" state, D3 indicates the "Off" state, and D1 and D2 represent power managed states. In the AIC-6915, three states are supported. D0 and D3 are required states and D2 is an optional state. Table 4-1 shows the states supported by the AIC-6915. Device States D0 D2 D3 Table 4-1. Power Management States Function Context Power Supported Action to Function Supported Actions from Function Implementation in PCI Module All context is retained Full power Any PCI transaction Any PCI Regular power and transaction or clocks interrupt All PCI configuration registers and Receive module are retained Lower power than D0 PCI Configuration Access Wakeup event All clocks stop other than target module and Receive module. Target abort if not config cycle All PCI configuration registers are retained Lower power PCI than any other Configuration state Access No action All clocks stop other than target module. target abort if not config cycle The assertion of RST_ on the PCI bus always returns the PCI function to the D0 uninitialized power-on default state. Removing Vcc always transitions the function to the D3 state. All other function power state changes are made by software through the PMCSR register. When a function is not in the D0 state, the value of the Bus Master, Memory Space and I/O Space bits in the PCI Command register are ignored, along with all Memory and I/O accesses on the PCI bus. In the D1, D2, and D3 states, only PCI configuration space can be accessed. All the other functional blocks are stopped, including the PCI master submodule and the BAC module. For the device to start another transaction other than a configuration access, software must return that device to the D0 state. This is accomplished by setting the Powerstate bits in the PMCSR register to the D0 state, or by a wakeup event that is initiated by the Receive module. When the PCI module receives any transfer request from the Receive module, it generates a PME_ (Power Management Event) interrupt. Software then checks the power management status registers and sets the PowerState to D0 and activates the full power PCI bus access. PME_ can be enabled by setting PME_Support field in the PMC (Power Management Capabilities) register. When the POWERSTATE bits in PMCSR are being changed, the PCI module sends a state change request to all other modules to make sure there are no current of pending transfers. The power state can be changed only after acknowledgment is received from all modules. 4-8