Adaptec 1737100 Programmer Manual - Page 117
Type: R/W, Internal Registers Subgroup: Ethernet Functional Registers, Byte Address, C0h - C3h
UPC - 760884136362
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Register Descriptions Bit(s) 3:0 Table 7-57. RxCompletionQueue1Ctrl Register (Continued) Reset rw Value Description/Function r/w 0 RxCompletionQ1Threshold specifies a threshold equal to 4*RxCompletionQ1Threshold. If RxCompletionQ1ThresholdMode is '0' and the number of empty entries in receive queue 1 is less or equal to the threshold, an interrupt status bit is set. If RxCompletionQ1ThresholdMode is '1' and the number of valid completion entries in receive queue 1 is greater than or equal to the threshold, an interrupt status bit is set. RxCompletionQueue2Ctrl Type: R/W Internal Registers Subgroup: Ethernet Functional Registers Byte Address: C0h - C3h Table 7-58. RxCompletionQueue2Ctrl Register Reset Bit(s) rw Value Description/Function 31:8 r/w x RxCompletionQ2BaseAddress[31:8]: This field contains the starting address of the queue in host memory. It is written by the host driver during initialization and read by the AIC-6915. The amount of host memory allocated for the completion queue is either 4-KBytes or 8-KBytes (programmable by bit 5, receive completion size). The starting address must be aligned to a 256-byte boundary. 7 r/w 0 RxCompletionQ2_64bitAddress: This bit indicates if Receive Completion queue 1 is located in 64-bit address space. If so, the AIC-6915 PCI Master must use 64-bit addressing mode to access the queue. 6 r/w 0 RxCompletionQ2ProducerWe: When this bit is set, the software driver is able to write the receive completion queue producer index. Otherwise, writes to the index are disabled. 5:4 r/w 0 RxCompletionQ2Type[1:0]: Controls the type of the completion descriptor. '00' - One word completion entry. '01' - Two word completion entry. The second word contains extended status and the VLAN ID and priority. '10' - Two word completion entry. The second word contains a partial checksum and 4 status bits. '11' - Four word completion entry. The entry contains a timestamp, full status, VLAN ID and priority, and the partial checksum. 3:0 r/w 0 RxCompletionQ2Threshold specifies a threshold equals to 4*RxCompletionQ2Threshold. If RxCompletionQ2ThresholdMode is '0' and the number of empty entries in receive queue 1 is less or equal to the threshold, an interrupt status bit is set. If RxCompletionQ2ThresholdMode is '1' and the number of valid completion entries in receive queue 1 is equal to or more than the threshold, an interrupt status bit is set. 7-45