Adaptec 1737100 Programmer Manual - Page 82
Pci Mwric, Mrdlc, Mrdmc, Cachesize[7:0], Pci_pcirst
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AIC-6915 Ethernet LAN Controller Programmer's Manual PCI Baseclass Register Type: R Internal Registers Subgroup: PCI Configuration Header Byte Address: 0Bh Table 7-10. BaseClass Register Reset Bit(s) rw value Description/Function 7:0 r 02h BASECLASS[7:0]: The BaseClass register identifies which base class the PCI device has been assigned to. The BASECLASS for the first version of the AIC-6915 is identified as 02h (Network controller). This value can be changed to a value read from an external serial EEPROM if the BR_A1 pin is '1' when PCI_PCIRST_ is deasserted. PCI Cachesize (Cache Line Size) Register Type: R/W Internal Registers Subgroup: PCI Configuration Header Byte Address: 0Ch The Cache Size register specifies the system cache line size in units of 32-bit words. The value stored in the register defines the minimum data transfer size and associated cache starting boundary (and multiples there of) that may be performed with cache line referenced PCI MWRIC, MRDLC or MRDMC commands. CACHESIZE[7:0] are reset to 0h during assertion of PCI_PCIRST_. Bit(s) rw 7:0 r/w Reset Value 0 Table 7-11. Cache Line Size Register Description/Function CACHESIZE[7:0]: Cache Size [7:0] defines the cache line size (in 32bit words). Those word values supported are: 0, 4, 8, 16, 32 and 64. Any other value is treated as CACHESIZE = 0. When CACHESIZE = 0, MWRIC is disabled. PCI Lattime (Latency Timer) Register Type: R/W Internal Registers Subgroup: PCI Configuration Header Byte Address: 0Dh Table 7-12. Latency Timer Register Reset Bit(s) rw Value Description/Function 7:2 r/w 10 LATTIME[7:2]: These bits determine the bus master latency timer period (in PCLK periods) of the AIC-6915. 1:0 r 0 LATTIME[1:0]: Always read 0 (sets granularity at four CLKs). 7-10
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