Adaptec 1737100 Programmer Manual - Page 40

AIC-6915 Ethernet LAN Controller Programmer's Manual Table 3-6. Type 4 Transmit DMA Descriptor (32-bit Addressing only) 31 24 23 16 15 8 7 0 Skip Field (multiple of 8 bytes) One Skip Field per Packet ID = 4'b1011 I ECC NNAR T DL C R TE CN P Reserved Reserved First Buffer Length First Buffer Address Reserved Number Of Tx Buffers Total Packet Length Last Buffer Length Last Buffer Address Reserved Transmit Completion Queue Entry Transmit Completion Queue entries consist of two types: DMA Complete Entry and Transmit Complete Entry, differentiated by the MSB of the entry. Three bits are defined in the "Type" field because the AIC-6915 always returns a nonzero value in the DMA Complete Entry. Each Transmit Completion Queue Entry can be programmed as either 4 bytes or 8 bytes. Table 3-7. Transmit Completion Queue Entry Type = DMA Complete Entry 31 29 28 16 15 14 0 Type Time Stamp Pr Index i s Type - 3 bit. Always 3'b100 for DMA Complete Entry. s Time Stamp - 13 bits. These are the 13 least significant bits of the 32-bit timer. These bits are sampled when the completion descriptor is formed after the complete DMAtransfer of the whole frame from host memory. s Pri - 1 bit. Indicates a high- or low-priority queue. s Index - 15 bits. Descriptor Queue Consumer Index points to the beginning of a packet in the Descriptor Queue. Its an 8 byte index, incremented by 1 every 8 bytes. If the buffer/frame descriptor has a Skip field, the index points to the beginning of the Skip field. 3-10